22nm_PowerPI.mdwn

   1 # Specs for 22/28nm SOC
   2
   3 **Overall goal: an SoC that is capable of meeting multiple markets:**
   4
   5 * Basic "Pi" style SBC role (aka POWER-Pi)
   6   - Power consumption to be **strictly** limited to under 3.5 watts
   7     so as to be passively-cooled and significantly reduce product costs,
   8     as well as increase reliability
   9 * Libre-style smartphone, tablet, netbook and chromebook products
  10   - Pine64, Purism, FairPhone, many others
  11   - 3.5 watt limit greatly simplifies portable product development,
  12     as well as increasing battery life
  13 * Baseboard Management Controller (BMC) replacement for ASpeed products
  14   - including PCIe Video Card capability after BMC Boot
  15 * Mid-end low-cost Graphics Card with reasonable 3D and VPU capabilities
  16   - This as a sub-goal of the BMC functionality (stand-alone)
  17
  18 By meeting the needs of multiple markets in a single SoC the product has
  19 broader appeal yet amortises the NREs across all of them.  This is
  20 industry-standard practice: ST Micro and ATMEL use the exact same die in
  21 up to 12-14 different products.
  22
  23 **Three different pin packages:**
  24
  25 * 400-450 pin FBGA 18mm 0.8mm and 14mm 0.6mm pitch
  26   - single 32-bit DDR3/4 interface.
  27   - Suitable for smaller products.
  28   - 0.8mm pitch is easier for low-cost China PCB manufacturing
  29   - This lesson is learned from Freescale's 19-year-LTS iMX6 SoC
  30 * 600-650 pin FPGA appx 20mm 0.6mm pitch
  31   - dual 32-bit DDR3/4 interfaces.
  32   - Suitable for 4k HD resolution screens and Graphics Card capability.
  33
  34 **Timeframe from when funding is received:**
  35
  36 * 6-8 months for PHY negotiation and supply by IP Vendors (DDR4 is always
  37   custom-tailored by the supplier)
  38 * 6-8 months development (in parallel with PHY negotiation)
  39 * 3-4 months FPGA proof-of-concept (partial overlap with above)
  40 * 4-6 months layout development once design is frozen (partial overlap with
  41   above)
  42
  43 Total: 12-18 months development time.  **This is industry-standard**
  44
  45 **NREs:**
  46
  47 These are ballpark estimates:
  48
  49 * USD 250,000 for layout software licensing (Cadence / Synopsis / Mentor)
  50 * USD 400,000 for engineer to perform layout to GDS-II
  51 * USD 1,000,000 for (LP)DDR3/4 which includes customisation by IP vendor
  52 * USD 250,000 for Libre-licensed DDR firmware (normally closed binary)
  53 * USD 250,000 for USB3/C
  54 * USD 250,000 for HDMI PHY (includes HDCP closed firmware: DVI may be better)
  55 * USD 50,000 for PCIe PHY
  56 * USD 50,000 for RGMII Ethernet PHY
  57 * USD 50,000 for Libre-licensed PCIe firmware (normally closed binary)
  58 * USD 2,000,000 for Engineers
  59 * USD 2,000,000 for 22nm Production Masks (1,000,000 for 28nm)
  60 * USD 200,000 per 22nm MPW Shuttle Service (test ASICs.  28nm is 100,000)
  61 * USD 200,000 estimated for other PHYs (UART, SD/MMC, I2C, SPI)
  62
  63 Total is around USD 7 million.
  64
  65 Note that this is a bare minimum and may require re-spins of the production
  66 masks.  A safety margin is recommended to cover at least 2 additional
  67 re-spins.  Business Operating costs bring the total realistically
  68 to around USD 12 million.
  69
  70 Production cost is expected to be around the $3.50 to $4 mark meaning
  71 that a sale price of around $12-$13 will require **1 million units**
  72 sold to recover the NREs.
  73
  74 **Even if the SoC used an off-the-shelf OpenPOWER core these development
  75 NREs are still required**
  76
  77 # Functionality
  78
  79  - 4 Core dual-issue LibreSOC OpenPOWER CPU
  80  - SimpleV Capability with VPU and GPU Instructions *no need for separate GPU*
  81  - IOMMU
  82  - PCIe Host Controller
  83  - PCIe Slave controller (RaptorCS wants to use LibreSOC as a Graphics Card
  84     on their TALOS-II motherboards)
  85  - BMC capability (OpenBMC / LibreBMC) - enables LibreSOC to replace the
  86    closed source ASpeed BMC product range, booting up large servers
  87    securely
  88  - RGB/TTL framebuffer VGA/LCD PHY from Richard Herveille, RoaLogic.
  89  - Pinmux for mapping multiple I/O functions to pins (standard fare
  90    for SoCs, to reduce pincount)
  91  - SD/MMC and eMMC
  92  - Standard "Pi / Arduino" SoC-style interfaces including UART, I2C,
  93    SPI, GPIO, PWM, EINT, AC97.
  94
  95 # Interfaces
  96
  97 ## Advanced
  98
  99  - SERDES - 10rx, 14tx
 100    - 4tx, 4rx for [OMI(DDR4](https://openpowerfoundation.org/wp-content/uploads/2018/10/Jeff-Steuchli.OpenCAPI-OPS-OMI.pdf) on top of SERDES with OpenCAPI protocol) @5GHz
 101    - 4tx, 4rx for PCIe and other CAPI devices
 102    - 3tx for HDMI (note: requires HDMI Trademark Licensing and Compliance Testing.  DVI is an alternative)
 103  - [OpenFSI](https://openpowerfoundation.org/?resource_lib=field-replaceable-unit-fru-service-interface-fsi-openfsi-specification) instead of JTAG
 104    - [Raptor HDL](https://gitlab.raptorengineering.com/raptor-engineering-public/lpc-spi-bridge-fpga)
 105    - [Raptor Libsigrok](https://gitlab.raptorengineering.com/raptor-engineering-public/dsview/-/tree/master/libsigrokdecode4DSL/decoders/fsi)
 106  - USB-OTG / USB2 - [Luna USB](https://github.com/greatscottgadgets/luna)
 107 with [USB3300 PHY](https://www.microchip.com/wwwproducts/en/USB3300#datasheet-toggle) (Tested max at 333MB/s with Luna on ECP5)
 108  - [[shakti/m_class/USB3]]
 109
 110 ## Basic
 111
 112 These should be easily doable with LiteX.
 113
 114 * [[shakti/m_class/UART]]
 115 * [[shakti/m_class/I2C]]
 116 * [[shakti/m_class/GPIO]]
 117 * [[shakti/m_class/SPI]]
 118 * [[shakti/m_class/QSPI]]
 119 * [[shakti/m_class/LPC]] - BMC Management
 120 * [[shakti/m_class/EINT]]
 121 * [[shakti/m_class/PWM]]
 122 * [[shakti/m_class/RGBTTL]] in conjunction with:
 123   - TI TFP410a (DVI / HDMI)
 124   - Chrontel converter (DVI, eDP, VGA)
 125   - Solomon SSD2828 (MIP)
 126   - TI SN75LVDS83b (LVDS)
 127
 128 # Protocols
 129  - IMPI over i2c to talk to the BMC
 130    - [Intel Spec Sheet](https://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/second-gen-interface-spec-v2.pdf)
 131    - [RaptorCS HDL](https://gitlab.raptorengineering.com/raptor-engineering-public/lpc-spi-bridge-fpga/blob/master/ipmi_bt_slave.v)
 132  - Reset Vector is set Flexver address over LPC
 133    - [Whitepaper](https://www.raptorengineering.com/TALOS/documentation/flexver_intro.pdf)