[libre-riscv-dev] Some recent documenting of work performed for tape-out
[libre-riscv-dev.git] / 37 / 0e4651bc080eb2ce3172e445317ead364451ad
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39 Subject: Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture
40 feasibility
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69 Lauri Kasanen schreef op ma 16-03-2020 om 09:14 [+0200]:
70 > On Sun, 15 Mar 2020 12:43:45 -0700Jacob Lifshay <programmerjake@gmail.com=
71 > wrote:
72 > > Later (for Libre-SOC v2 or v3), it might be a good idea to add support =
73 forx86 and x86_64 user-mode since the patents for the base ISA will haveexp=
74 ired by then. This would help give us an advantage since it would allowus t=
75 o run legacy software.
76 >=20
77 > 486 and 586 patents had expired years ago, and we had Chinese 1 GHzimplem=
78 entations of those (vortex86). Now they have 686 models, so Itake pentium p=
79 ro patents are also up for use.
80
81 I think these were because Via had cross-patent license agreement with Inte=
82 l.
83
84 greets,
85 Staf.
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