50/d0e13005b742e3f06badca9b2f4f35a663d96a

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  11  for libre-riscv-dev@lists.libre-riscv.org; Tue, 09 Jun 2020 23:53:27 +0100
  12 From: bugzilla-daemon@libre-soc.org
  13 To: libre-riscv-dev@lists.libre-riscv.org
  14 Date: Tue, 09 Jun 2020 22:53:28 +0000
  15 X-Bugzilla-Reason: CC
  16 X-Bugzilla-Type: changed
  17 X-Bugzilla-Watch-Reason: None
  18 X-Bugzilla-Product: Libre-SOC's first SoC
  19 X-Bugzilla-Component: Source Code
  20 X-Bugzilla-Version: unspecified
  21 X-Bugzilla-Keywords:
  22 X-Bugzilla-Severity: enhancement
  23 X-Bugzilla-Who: lkcl@lkcl.net
  24 X-Bugzilla-Status: CONFIRMED
  25 X-Bugzilla-Resolution:
  26 X-Bugzilla-Priority: Low
  27 X-Bugzilla-Assigned-To: programmerjake@gmail.com
  28 X-Bugzilla-Flags:
  29 X-Bugzilla-Changed-Fields: cc
  30 Message-ID: <bug-372-13-Bp6ZFTV5Xy@https.bugs.libre-soc.org/>
  31 In-Reply-To: <bug-372-13@https.bugs.libre-soc.org/>
  32 References: <bug-372-13@https.bugs.libre-soc.org/>
  33 X-Bugzilla-URL: https://bugs.libre-soc.org/
  34 Auto-Submitted: auto-generated
  35 MIME-Version: 1.0
  36 Subject: [libre-riscv-dev] [Bug 372] create cycle-accurate
  37  JIT-compiler-based processor simulator
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