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  22 Message-ID: <686f9b58ae6f6a3e11caff9714db66a0406e8b0b.camel@lip6.fr>
  23 From: Jean-Paul Chaput <Jean-Paul.Chaput@lip6.fr>
  24 To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
  25 Date: Tue, 24 Mar 2020 13:23:36 +0100
  26 In-Reply-To: <0F80A1BC-0241-49FE-B374-B4F1D8F3F5BD@gatech.edu>
  27 References: <0F80A1BC-0241-49FE-B374-B4F1D8F3F5BD@gatech.edu>
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  35 Subject: Re: [libre-riscv-dev] Advanced Topics on RISCV
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  63
  64
  65
  66 Hello Immanuel,
  67
  68 About manycores, we did a lot of work on that topic in our lab
  69 (Sorbonne Universit=C3=A9/LIP6). I send you a reference toward the
  70 project we developed. This is a huge lot of work and may take
  71 a lot of time to understand. But, we made a real chip with
  72 16 cores to prove it works (and it do work). I cannot give you
  73 more technical information as it not my field of expertise.
  74
  75 You must distinguish two case:
  76
  77 * Multi cores ( < 16) in that case, simpler solutions can be
  78   used.
  79
  80 * Many cores ( > 16) in this case, the TSAR project can be
  81   of interest.
  82
  83 TSAR (Tera-Scale ARchitecture).
  84
  85 You can see details here:
  86     https://www-soc.lip6.fr/trac/tsar
  87
  88 Best regards,
  89
  90
  91 PS: Already signaled it to Luke.
  92
  93
  94 On Tue, 2020-03-24 at 11:51 +0000, Immanuel, Yehowshua U wrote:
  95 > I=E2=80=99ve read through the Spike page and a good portion of the simple=
  96 V page.
  97 >=20
  98 > My two goals at the moment are:
  99 > 1. Understand how RISCV handles multiple processes and does page walking
 100 > 2. Understand how multicore ROSCV would work
 101 >=20
 102 > I=E2=80=99m hoping to play with FreeRTOS soon so I can run through its co=
 103 debase for setting up
 104 > page tables.
 105 > Also, do you know if spike tests the special instructions like exception =
 106 instructions?
 107 > Also, what RISCV instructions would a kernel use to set up the pagetables=
 108 ?
 109 >=20
 110 > Lastly, do you know any good resources for intro to multicore systems? RI=
 111 SCV doesn=E2=80=99t
 112 > seem to have any multicore specific instructions. My current questions wo=
 113 uld include
 114 > things like:
 115 >=20
 116 > 1. How can the kernel assign tasks to a certain core? If you have a proce=
 117 ss with
 118 > multiple threads, it would make sense to spread out the threads among ava=
 119 ilable
 120 > processors instead of concentrating them on a single core. How might this=
 121  work with
 122 > respect to RISCV?
 123 >=20
 124 > 2. Does the hardware ensure cache coherency - that is - externally - soft=
 125 ware sees one
 126 > big cache all though I imagine each core would have a local cache that wo=
 127 uld have to
 128 > communicate with other caches?
 129 >=20
 130 > Yehowshua
 131 > _______________________________________________
 132 > libre-riscv-dev mailing list
 133 > libre-riscv-dev@lists.libre-riscv.org
 134 > http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev
 135 --=20
 136
 137       .-.     J e a n - P a u l   C h a p u t  /  Administrateur Systeme
 138       /v\     Jean-Paul.Chaput@lip6.fr
 139     /(___)\   work: (33) 01.44.27.53.99             =20
 140      ^^ ^^    cell:      06.66.25.35.55   home: 09.65.29.83.38
 141
 142     U P M C   Universite Pierre & Marie Curie
 143     L I P 6   Laboratoire d'Informatique de Paris VI
 144     S o C     System On Chip
 145
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