7e/4388e1816057a32c8bec1313753b89a1bb6810

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  13 To: libre-riscv-dev@lists.libre-riscv.org
  14 Date: Thu, 26 Mar 2020 11:02:24 +0000
  15 X-Bugzilla-Reason: CC
  16 X-Bugzilla-Type: changed
  17 X-Bugzilla-Watch-Reason: None
  18 X-Bugzilla-Product: Libre-SOC's first SoC
  19 X-Bugzilla-Component: Specification
  20 X-Bugzilla-Version: unspecified
  21 X-Bugzilla-Keywords:
  22 X-Bugzilla-Severity: enhancement
  23 X-Bugzilla-Who: lkcl@lkcl.net
  24 X-Bugzilla-Status: CONFIRMED
  25 X-Bugzilla-Resolution:
  26 X-Bugzilla-Priority: ---
  27 X-Bugzilla-Assigned-To: lkcl@lkcl.net
  28 X-Bugzilla-Flags:
  29 X-Bugzilla-Changed-Fields:
  30 Message-ID: <bug-186-13-HmItjmDZGW@http.bugs.libre-riscv.org/>
  31 In-Reply-To: <bug-186-13@http.bugs.libre-riscv.org/>
  32 References: <bug-186-13@http.bugs.libre-riscv.org/>
  33 X-Bugzilla-URL: http://bugs.libre-riscv.org/
  34 Auto-Submitted: auto-generated
  35 MIME-Version: 1.0
  36 Subject: [libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and
  37  RISC-V
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