[libre-riscv-dev] Some recent documenting of work performed for tape-out
[libre-riscv-dev.git] / 89 / 52b2442d05dd48bdfcb3e04276a2b7b948273e
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59 Luke Kenneth Casson Leighton schreef op vr 08-05-2020 om 10:08 [+0100]:
60 > > 0.18um TSMC MPW runs are done at least once a month. You can find the s=
61 chedule online: https://europractice-ic.com/wp-content/uploads/2020/05/Gene=
62 ral-MPW-EUROPRACTICE-200505-v8.pdf
63 >=20
64 > so everyone is aware: these general 180nm MPW runs are not EUR 600 /sq.mm=
65 (the subsidised cost via Staf). they're 2-3x that level: aroundEUR 1100 t=
66 o 1500
67 >=20
68 > Yehowshua wrote:
69 > > And worst case scenario, I can acquire the needed funds for testing the=
70 chip from alternative funding sources no problem.
71 >=20
72 > this is good - it would however not be at the EUR 600 / sq.mm level,it wo=
73 uld be at double that, and also likely need Staf's paid-forassistance (if y=
74 ou're up for that, Staf?) to act as a firebreak forthe NDAs.
75
76 I don't subsidize the MPW runs I just charge the imec price to NLNet. I don=
77 't include normal industrial markup on the price for NLNet and just charge =
78 the (projected) time needed for the tape-out.
79 The cost is a little over the =E2=82=AC600/mm=C2=B2 without packaging of th=
80 e chips. For TSMC tape-out there is a minimum area charge of 25mm=C2=B2. Fo=
81 r packaging you can go for semi-automatic packaging with a high cost per ch=
82 ip; prices are here. For high volume you have low per unit packaging cost (=
83 <$0.5/unit) but a start-up cost of over $5000.
84
85 greets,
86 Staf.
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