CHANGELOG

   1
   2 List of major changes and improvements between releases
   3 =======================================================
   4
   5 Yosys 0.17 .. Yosys 0.17-dev
   6 --------------------------
   7  * Formal Verification
   8     - Fixed the signedness of $past's return value to be the same as the
   9       argument's instead of always unsigned.
  10
  11  * Verilog
  12     - Fixed an issue where simplifying case statements by removing unreachable
  13       cases could result in the wrong signedness being used for comparison with
  14       the remaining cases
  15     - Fixed size and signedness computation for expressions containing array
  16       querying functions
  17     - Fixed size and signedness computation of functions used in ternary
  18       expressions or case item expressions
  19
  20 Yosys 0.16 .. Yosys 0.17
  21 --------------------------
  22  * New commands and options
  23     - Added "write_jny" ( JSON netlist metadata format )
  24     - Added "tribuf -formal"
  25
  26  * SystemVerilog
  27     - Fixed automatic `nosync` inference for local variables in `always_comb`
  28       procedures not applying to nested blocks and blocks in functions
  29
  30 Yosys 0.15 .. Yosys 0.16
  31 --------------------------
  32  * Various
  33     - Added BTOR2 witness file co-simulation.
  34     - Simulation calls external vcd2fst for VCD conversion.
  35     - Added fst2tb pass - generates testbench for the circuit using
  36       the given top-level module and simulus signal from FST file.
  37     - yosys-smtbmc: Option to keep going after failed assertions in BMC mode
  38
  39  * Verific support
  40     - Import modules in alphabetic (reproducable) order.
  41
  42 Yosys 0.14 .. Yosys 0.15
  43 --------------------------
  44
  45  * Various
  46     - clk2fflogic: nice names for autogenerated signals
  47     - simulation include support for all flip-flop types.
  48     - Added AIGER witness file co-simulation.
  49
  50  * Verilog
  51     - Fixed evaluation of constant functions with variables or arguments with
  52       reversed dimensions
  53     - Fixed elaboration of dynamic range assignments where the vector is
  54       reversed or is not zero-indexed
  55     - Added frontend support for time scale delay values (e.g., `#1ns`)
  56
  57  * SystemVerilog
  58     - Added support for accessing whole sub-structures in expressions
  59
  60  * New commands and options
  61     - Added glift command, used to create gate-level information flow tracking
  62       (GLIFT) models by the "constructive mapping" approach
  63
  64  * Verific support
  65     - Ability to override default parser mode for verific -f command.
  66
  67 Yosys 0.13 .. Yosys 0.14
  68 --------------------------
  69
  70  * Various
  71     - Added $bmux and $demux cells and related optimization patterns.
  72
  73  * New commands and options
  74     - Added "bmuxmap" and "dmuxmap" passes
  75     - Added "-fst" option to "sim" pass for writing FST files
  76     - Added "-r", "-scope", "-start", "-stop", "-at", "-sim", "-sim-gate",
  77       "-sim-gold" options to "sim" pass for co-simulation
  78
  79  * Anlogic support
  80     - Added support for BRAMs
  81
  82 Yosys 0.12 .. Yosys 0.13
  83 --------------------------
  84
  85  * Various
  86     - Use "read" command to parse HDL files from Yosys command-line
  87     - Added "yosys -r <topmodule>" command line option
  88     - write_verilog: dump zero width sigspecs correctly
  89
  90  * SystemVerilog
  91     - Fixed regression preventing the use array querying functions in case
  92       expressions and case item expressions
  93     - Fixed static size casts inadvertently limiting the result width of binary
  94       operations
  95     - Fixed static size casts ignoring expression signedness
  96     - Fixed static size casts not extending unbased unsized literals
  97     - Added automatic `nosync` inference for local variables in `always_comb`
  98       procedures which are always assigned before they are used to avoid errant
  99       latch inference
 100
 101  * New commands and options
 102     - Added "clean_zerowidth" pass
 103
 104  * Verific support
 105     - Add YOSYS to the implicitly defined verilog macros in verific
 106
 107 Yosys 0.11 .. Yosys 0.12
 108 --------------------------
 109
 110  * Various
 111     - Added iopadmap native support for negative-polarity output enable
 112     - ABC update
 113
 114  * SystemVerilog
 115     - Support parameters using struct as a wiretype
 116
 117  * New commands and options
 118     - Added "-genlib" option to "abc" pass
 119     - Added "sta" very crude static timing analysis pass
 120
 121  * Verific support
 122     - Fixed memory block size in import
 123
 124  * New back-ends
 125     - Added support for GateMate FPGA from Cologne Chip AG
 126
 127  * Intel ALM support
 128     - Added preliminary Arria V support
 129
 130
 131 Yosys 0.10 .. Yosys 0.11
 132 --------------------------
 133
 134  * Various
 135     - Added $aldff and $aldffe (flip-flops with async load) cells
 136
 137  * SystemVerilog
 138     - Fixed an issue which prevented writing directly to a memory word via a
 139       connection to an output port
 140     - Fixed an issue which prevented unbased unsized literals (e.g., `'1`) from
 141       filling the width of a cell input
 142     - Fixed an issue where connecting a slice covering the entirety of a signed
 143       signal to a cell input would cause a failed assertion
 144
 145  * Verific support
 146     - Importer support for {PRIM,WIDE_OPER}_DFF
 147     - Importer support for PRIM_BUFIF1
 148     - Option to use Verific without VHDL support
 149     - Importer support for {PRIM,WIDE_OPER}_DLATCH{,RS}
 150     - Added -cfg option for getting/setting Verific runtime flags
 151
 152 Yosys 0.9 .. Yosys 0.10
 153 --------------------------
 154
 155  * Various
 156     - Added automatic gzip decompression for frontends
 157     - Added $_NMUX_ cell type
 158     - Added automatic gzip compression (based on filename extension) for backends
 159     - Improve attribute and parameter encoding in JSON to avoid ambiguities between
 160       bit vectors and strings containing [01xz]*
 161     - Improvements in pmgen: subpattern and recursive matches
 162     - Support explicit FIRRTL properties
 163     - Improvements in pmgen: slices, choices, define, generate
 164     - Added "_TECHMAP_WIREINIT_*_" parameter and "_TECHMAP_REMOVEINIT_*_" wire for "techmap" pass
 165     - Added +/mul2dsp.v for decomposing wide multipliers to custom-sized ones
 166     - Added new frontend: rpc
 167     - Added --version and -version as aliases for -V
 168     - Improve yosys-smtbmc "solver not found" handling
 169     - Improved support of $readmem[hb] Memory Content File inclusion
 170     - Added CXXRTL backend
 171     - Use YosysHQ/abc instead of upstream berkeley-abc/abc
 172     - Added WASI platform support.
 173     - Added extmodule support to firrtl backend
 174     - Added $divfloor and $modfloor cells
 175     - Added $adffe, $dffsre, $sdff, $sdffe, $sdffce, $adlatch cells
 176     - Added "_TECHMAP_CELLNAME_" parameter for "techmap" pass
 177     - Added firrtl backend support for generic parameters in blackbox components
 178     - Added $meminit_v2 cells (with support for write mask)
 179     - Added $mem_v2, $memrd_v2, $memwr_v2, with the following features:
 180       - write priority masks, per write/write port pair
 181       - transparency and undefined collision behavior masks, per read/write port pair
 182       - read port reset and initialization
 183       - wide ports (accessing a naturally aligned power-of-two number of memory cells)
 184
 185  * New commands and options
 186     - Added "write_xaiger" backend
 187     - Added "read_xaiger"
 188     - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only)
 189     - Added "synth -abc9" (experimental)
 190     - Added "script -scriptwire"
 191     - Added "clkbufmap" pass
 192     - Added "extractinv" pass and "invertible_pin" attribute
 193     - Added "proc_clean -quiet"
 194     - Added "proc_prune" pass
 195     - Added "stat -tech cmos"
 196     - Added "opt_share" pass, run as part of "opt -full"
 197     - Added "-match-init" option to "dff2dffs" pass
 198     - Added "equiv_opt -multiclock"
 199     - Added "techmap_autopurge" support to techmap
 200     - Added "add -mod <modname[s]>"
 201     - Added "paramap" pass
 202     - Added "portlist" command
 203     - Added "check -mapped"
 204     - Added "check -allow-tbuf"
 205     - Added "autoname" pass
 206     - Added "write_verilog -extmem"
 207     - Added "opt_mem" pass
 208     - Added "scratchpad" pass
 209     - Added "fminit" pass
 210     - Added "opt_lut_ins" pass
 211     - Added "logger" pass
 212     - Added "show -nobg"
 213     - Added "exec" command
 214     - Added "design -delete"
 215     - Added "design -push-copy"
 216     - Added "qbfsat" command
 217     - Added "select -unset"
 218     - Added "dfflegalize" pass
 219     - Removed "opt_expr -clkinv" option, made it the default
 220     - Added "proc -nomux
 221     - Merged "dffsr2dff", "opt_rmdff", "dff2dffe", "dff2dffs", "peepopt.dffmux" passes into a new "opt_dff" pass
 222
 223  * SystemVerilog
 224     - Added checking of always block types (always_comb, always_latch and always_ff)
 225     - Added support for wildcard port connections (.*)
 226     - Added support for enum typedefs
 227     - Added support for structs and packed unions.
 228     - Allow constant function calls in for loops and generate if and case
 229     - Added support for static cast
 230     - Added support for logic typed parameters
 231     - Fixed generate scoping issues
 232     - Added support for real-valued parameters
 233     - Allow localparams in constant functions
 234     - Module name scope support
 235     - Support recursive functions using ternary expressions
 236     - Extended support for integer types
 237     - Support for parameters without default values
 238     - Allow globals in one file to depend on globals in another
 239     - Added support for: *=, /=, %=, <<=, >>=, <<<=, >>>=
 240     - Added support for parsing the 'bind' construct
 241     - support declaration in procedural for initialization
 242     - support declaration in generate for initialization
 243     - Support wand and wor of data types
 244
 245  * Verific support
 246     - Added "verific -L"
 247     - Add Verific SVA support for "always" properties
 248     - Add Verific support for SVA nexttime properties
 249     - Improve handling of verific primitives in "verific -import -V" mode
 250     - Import attributes for wires
 251     - Support VHDL enums
 252     - Added support for command files
 253
 254  * New back-ends
 255     - Added initial EFINIX support
 256     - Added Intel ALM: alternative synthesis for Intel FPGAs
 257     - Added initial Nexus support
 258     - Added initial MachXO2 support
 259     - Added initial QuickLogic PolarPro 3 support
 260
 261  * ECP5 support
 262     - Renamed labels/options in synth_ecp5 (e.g. dram -> map_lutram; -nodram -> -nolutram)
 263     - Added "synth_ecp5 -abc9" (experimental)
 264     - Added "synth_ecp5 -nowidelut"
 265     - "synth_ecp5" to now infer DSP blocks (-nodsp to disable, experimental)
 266
 267  * iCE40 support
 268     - Added "synth_ice40 -abc9" (experimental)
 269     - Added "synth_ice40 -device"
 270     - Renamed labels/options in synth_ice40 (e.g. dram -> map_lutram; -nodram -> -nolutram)
 271     - Added "ice40_wrapcarry" to encapsulate SB_LUT+SB_CARRY pairs for techmapping
 272     - Removed "ice40_unlut"
 273     - Added "ice40_dsp" for Lattice iCE40 DSP packing
 274     - "synth_ice40 -dsp" to infer DSP blocks
 275
 276  * Xilinx support
 277     - Added "synth_xilinx -abc9" (experimental)
 278     - Added "synth_xilinx -nocarry"
 279     - Added "synth_xilinx -nowidelut"
 280     - "synth_xilinx" to now infer wide multiplexers (-widemux <min> to enable)
 281     - Renamed labels/options in synth_xilinx (e.g. dram -> map_lutram; -nodram -> -nolutram)
 282     - Added "synth_xilinx -family xc6s" for Spartan 6 support (experimental)
 283     - Added "synth_xilinx -ise" (experimental)
 284     - Added "synth_xilinx -iopad"
 285     - "synth_xilinx" now automatically inserts clock buffers (add -noclkbuf to disable)
 286     - Added "xilinx_srl" for Xilinx shift register extraction
 287     - Removed "shregmap -tech xilinx" (superseded by "xilinx_srl")
 288     - Added "xilinx_dsp" for Xilinx DSP packing
 289     - "synth_xilinx" to now infer DSP blocks (-nodsp to disable)
 290     - Added latch support to synth_xilinx
 291     - Added support for flip-flops with synchronous reset to synth_xilinx
 292     - Added support for flip-flops with reset and enable to synth_xilinx
 293     - Added "xilinx_dffopt" pass
 294     - Added "synth_xilinx -dff"
 295
 296  * Intel support
 297     - Renamed labels in synth_intel (e.g. bram -> map_bram)
 298     - synth_intel: cyclone10 -> cyclone10lp, a10gx -> arria10gx
 299     - Added "intel_alm -abc9" (experimental)
 300
 301  * CoolRunner2 support
 302     - Separate and improve buffer cell insertion pass
 303     - Use extract_counter to optimize counters
 304
 305 Yosys 0.8 .. Yosys 0.9
 306 ----------------------
 307
 308  * Various
 309     - Many bugfixes and small improvements
 310     - Added support for SystemVerilog interfaces and modports
 311     - Added "write_edif -attrprop"
 312     - Added "opt_lut" pass
 313     - Added "gate2lut.v" techmap rule
 314     - Added "rename -src"
 315     - Added "equiv_opt" pass
 316     - Added "flowmap" LUT mapping pass
 317     - Added "rename -wire" to rename cells based on the wires they drive
 318     - Added "bugpoint" for creating minimised testcases
 319     - Added "write_edif -gndvccy"
 320     - "write_verilog" to escape Verilog keywords
 321     - Fixed sign handling of real constants
 322     - "write_verilog" to write initial statement for initial flop state
 323     - Added pmgen pattern matcher generator
 324     - Fixed opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_
 325     - Added "setundef -params" to replace undefined cell parameters
 326     - Renamed "yosys -D" to "yosys -U", added "yosys -D" to set Verilog defines
 327     - Fixed handling of defparam when default_nettype is none
 328     - Fixed "wreduce" flipflop handling
 329     - Fixed FIRRTL to Verilog process instance subfield assignment
 330     - Added "write_verilog -siminit"
 331     - Several fixes and improvements for mem2reg memories
 332     - Fixed handling of task output ports in clocked always blocks
 333     - Improved handling of and-with-1 and or-with-0 in "opt_expr"
 334     - Added "read_aiger" frontend
 335     - Added "mutate" pass
 336     - Added "hdlname" attribute
 337     - Added "rename -output"
 338     - Added "read_ilang -lib"
 339     - Improved "proc" full_case detection and handling
 340     - Added "whitebox" and "lib_whitebox" attributes
 341     - Added "read_verilog -nowb", "flatten -wb" and "wbflip"
 342     - Added Python bindings and support for Python plug-ins
 343     - Added "pmux2shiftx"
 344     - Added log_debug framework for reduced default verbosity
 345     - Improved "opt_expr" and "opt_clean" handling of (partially) undriven and/or unused wires
 346     - Added "peepopt" peephole optimisation pass using pmgen
 347     - Added approximate support for SystemVerilog "var" keyword
 348     - Added parsing of "specify" blocks into $specrule and $specify[23]
 349     - Added support for attributes on parameters and localparams
 350     - Added support for parsing attributes on port connections
 351     - Added "wreduce -keepdc"
 352     - Added support for optimising $dffe and $_DFFE_* cells in "opt_rmdff"
 353     - Added Verilog wand/wor wire type support
 354     - Added support for elaboration system tasks
 355     - Added "muxcover -mux{4,8,16}=<cost>"
 356     - Added "muxcover -dmux=<cost>"
 357     - Added "muxcover -nopartial"
 358     - Added "muxpack" pass
 359     - Added "pmux2shiftx -norange"
 360     - Added support for "~" in filename parsing
 361     - Added "read_verilog -pwires" feature to turn parameters into wires
 362     - Fixed sign extension of unsized constants with 'bx and 'bz MSB
 363     - Fixed genvar to be a signed type
 364     - Added support for attributes on case rules
 365     - Added "upto" and "offset" to JSON frontend and backend
 366     - Several liberty file parser improvements
 367     - Fixed handling of more complex BRAM patterns
 368     - Add "write_aiger -I -O -B"
 369
 370  * Formal Verification
 371     - Added $changed support to read_verilog
 372     - Added "read_verilog -noassert -noassume -assert-assumes"
 373     - Added btor ops for $mul, $div, $mod and $concat
 374     - Added yosys-smtbmc support for btor witnesses
 375     - Added "supercover" pass
 376     - Fixed $global_clock handling vs autowire
 377     - Added $dffsr support to "async2sync"
 378     - Added "fmcombine" pass
 379     - Added memory init support in "write_btor"
 380     - Added "cutpoint" pass
 381     - Changed "ne" to "neq" in btor2 output
 382     - Added support for SVA "final" keyword
 383     - Added "fmcombine -initeq -anyeq"
 384     - Added timescale and generated-by header to yosys-smtbmc vcd output
 385     - Improved BTOR2 handling of undriven wires
 386
 387  * Verific support
 388     - Enabled Verific flags vhdl_support_variable_slice and veri_elaborate_top_level_modules_having_interface_ports
 389     - Improved support for asymmetric memories
 390     - Added "verific -chparam"
 391     - Fixed "verific -extnets" for more complex situations
 392     - Added "read -verific" and "read -noverific"
 393     - Added "hierarchy -chparam"
 394
 395  * New back-ends
 396     - Added initial Anlogic support
 397     - Added initial SmartFusion2 and IGLOO2 support
 398
 399  * ECP5 support
 400     - Added "synth_ecp5 -nowidelut"
 401     - Added BRAM inference support to "synth_ecp5"
 402     - Added support for transforming Diamond IO and flipflop primitives
 403
 404  * iCE40 support
 405     - Added "ice40_unlut" pass
 406     - Added "synth_ice40 -relut"
 407     - Added "synth_ice40 -noabc"
 408     - Added "synth_ice40 -dffe_min_ce_use"
 409     - Added DSP inference support using pmgen
 410     - Added support for initialising BRAM primitives from a file
 411     - Added iCE40 Ultra RGB LED driver cells
 412
 413  * Xilinx support
 414     - Use "write_edif -pvector bra" for Xilinx EDIF files
 415     - Fixes for VPR place and route support with "synth_xilinx"
 416     - Added more cell simulation models
 417     - Added "synth_xilinx -family"
 418     - Added "stat -tech xilinx" to estimate logic cell usage
 419     - Added "synth_xilinx -nocarry"
 420     - Added "synth_xilinx -nowidelut"
 421     - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
 422     - Added support for mapping RAM32X1D
 423
 424 Yosys 0.7 .. Yosys 0.8
 425 ----------------------
 426
 427  * Various
 428     - Many bugfixes and small improvements
 429     - Strip debug symbols from installed binary
 430     - Replace -ignore_redef with -[no]overwrite in front-ends
 431     - Added write_verilog hex dump support, add -nohex option
 432     - Added "write_verilog -decimal"
 433     - Added "scc -set_attr"
 434     - Added "verilog_defines" command
 435     - Remember defines from one read_verilog to next
 436     - Added support for hierarchical defparam
 437     - Added FIRRTL back-end
 438     - Improved ABC default scripts
 439     - Added "design -reset-vlog"
 440     - Added "yosys -W regex", "yosys -w regex", and "yosys -e regex"
 441     - Added Verilog $rtoi and $itor support
 442     - Added "check -initdrv"
 443     - Added "read_blif -wideports"
 444     - Added support for SystemVerilog "++" and "--" operators
 445     - Added support for SystemVerilog unique, unique0, and priority case
 446     - Added "write_edif" options for edif "flavors"
 447     - Added support for resetall compiler directive
 448     - Added simple C beck-end (bitwise combinatorical only atm)
 449     - Added $_ANDNOT_ and $_ORNOT_ cell types
 450     - Added cell library aliases to "abc -g"
 451     - Added "setundef -anyseq"
 452     - Added "chtype" command
 453     - Added "design -import"
 454     - Added "write_table" command
 455     - Added "read_json" command
 456     - Added "sim" command
 457     - Added "extract_fa" and "extract_reduce" commands
 458     - Added "extract_counter" command
 459     - Added "opt_demorgan" command
 460     - Added support for $size and $bits SystemVerilog functions
 461     - Added "blackbox" command
 462     - Added "ltp" command
 463     - Added support for editline as replacement for readline
 464     - Added warnings for driver-driver conflicts between FFs (and other cells) and constants
 465     - Added "yosys -E" for creating Makefile dependencies files
 466     - Added "synth -noshare"
 467     - Added "memory_nordff"
 468     - Added "setundef -undef -expose -anyconst"
 469     - Added "expose -input"
 470     - Added specify/specparam parser support (simply ignore them)
 471     - Added "write_blif -inames -iattr"
 472     - Added "hierarchy -simcheck"
 473     - Added an option to statically link abc into yosys
 474     - Added protobuf back-end
 475     - Added BLIF parsing support for .conn and .cname
 476     - Added read_verilog error checking for reg/wire/logic misuse
 477     - Added "make coverage" and ENABLE_GCOV build option
 478
 479  * Changes in Yosys APIs
 480     - Added ConstEval defaultval feature
 481     - Added {get,set}_src_attribute() methods on RTLIL::AttrObject
 482     - Added SigSpec::is_fully_ones() and Const::is_fully_ones()
 483     - Added log_file_warning() and log_file_error() functions
 484
 485  * Formal Verification
 486     - Added "write_aiger"
 487     - Added "yosys-smtbmc --aig"
 488     - Added "always <positive_int>" to .smtc format
 489     - Added $cover cell type and support for cover properties
 490     - Added $fair/$live cell type and support for liveness properties
 491     - Added smtbmc support for memory vcd dumping
 492     - Added "chformal" command
 493     - Added "write_smt2 -stbv" and "write_smt2 -stdt"
 494     - Fix equiv_simple, old behavior now available with "equiv_simple -short"
 495     - Change to Yices2 as default SMT solver (it is GPL now)
 496     - Added "yosys-smtbmc --presat" (now default in SymbiYosys)
 497     - Added "yosys-smtbmc --smtc-init --smtc-top --noinit"
 498     - Added a brand new "write_btor" command for BTOR2
 499     - Added clk2fflogic memory support and other improvements
 500     - Added "async memory write" support to write_smt2
 501     - Simulate clock toggling in yosys-smtbmc VCD output
 502     - Added $allseq/$allconst cells for EA-solving
 503     - Make -nordff the default in "prep"
 504     - Added (* gclk *) attribute
 505     - Added "async2sync" pass for single-clock designs with async resets
 506
 507  * Verific support
 508     - Many improvements in Verific front-end
 509     - Added proper handling of concurent SVA properties
 510     - Map "const" and "rand const" to $anyseq/$anyconst
 511     - Added "verific -import -flatten" and "verific -import -extnets"
 512     - Added "verific -vlog-incdir -vlog-define -vlog-libdir"
 513     - Remove PSL support (because PSL has been removed in upstream Verific)
 514     - Improve integration with "hierarchy" command design elaboration
 515     - Added YOSYS_NOVERIFIC for running non-verific test cases with verific bin
 516     - Added simpilied "read" command that automatically uses verific if available
 517     - Added "verific -set-<severity> <msg_id>.."
 518     - Added "verific -work <libname>"
 519
 520  * New back-ends
 521     - Added initial Coolrunner-II support
 522     - Added initial eASIC support
 523     - Added initial ECP5 support
 524
 525  * GreenPAK Support
 526     - Added support for GP_DLATCH, GP_SPI, GP_DCMx, GP_COUNTx, etc.
 527
 528  * iCE40 Support
 529     - Add "synth_ice40 -vpr"
 530     - Add "synth_ice40 -nodffe"
 531     - Add "synth_ice40 -json"
 532     - Add Support for UltraPlus cells
 533
 534  * MAX10 and Cyclone IV Support
 535     - Added initial version of metacommand "synth_intel".
 536     - Improved write_verilog command to produce VQM netlist for Quartus Prime.
 537     - Added support for MAX10 FPGA family synthesis.
 538     - Added support for Cyclone IV family synthesis.
 539     - Added example of implementation for DE2i-150 board.
 540     - Added example of implementation for MAX10 development kit.
 541     - Added LFSR example from Asic World.
 542     - Added "dffinit -highlow" for mapping to Intel primitives
 543
 544
 545 Yosys 0.6 .. Yosys 0.7
 546 ----------------------
 547
 548  * Various
 549     - Added "yosys -D" feature
 550     - Added support for installed plugins in $(DATDIR)/plugins/
 551     - Renamed opt_const to opt_expr
 552     - Renamed opt_share to opt_merge
 553     - Added "prep -flatten" and "synth -flatten"
 554     - Added "prep -auto-top" and "synth -auto-top"
 555     - Using "mfs" and "lutpack" in ABC lut mapping
 556     - Support for abstract modules in chparam
 557     - Cleanup abstract modules at end of "hierarchy -top"
 558     - Added tristate buffer support to iopadmap
 559     - Added opt_expr support for div/mod by power-of-two
 560     - Added "select -assert-min <N> -assert-max <N>"
 561     - Added "attrmvcp" pass
 562     - Added "attrmap" command
 563     - Added "tee +INT -INT"
 564     - Added "zinit" pass
 565     - Added "setparam -type"
 566     - Added "shregmap" pass
 567     - Added "setundef -init"
 568     - Added "nlutmap -assert"
 569     - Added $sop cell type and "abc -sop -I <num> -P <num>"
 570     - Added "dc2" to default ABC scripts
 571     - Added "deminout"
 572     - Added "insbuf" command
 573     - Added "prep -nomem"
 574     - Added "opt_rmdff -keepdc"
 575     - Added "prep -nokeepdc"
 576     - Added initial version of "synth_gowin"
 577     - Added "fsm_expand -full"
 578     - Added support for fsm_encoding="user"
 579     - Many improvements in GreenPAK4 support
 580     - Added black box modules for all Xilinx 7-series lib cells
 581     - Added synth_ice40 support for latches via logic loops
 582     - Fixed ice40_opt lut unmapping, added "ice40_opt -unlut"
 583
 584  * Build System
 585     - Added ABCEXTERNAL and ABCURL make variables
 586     - Added BINDIR, LIBDIR, and DATDIR make variables
 587     - Added PKG_CONFIG make variable
 588     - Added SEED make variable (for "make test")
 589     - Added YOSYS_VER_STR make variable
 590     - Updated min GCC requirement to GCC 4.8
 591     - Updated required Bison version to Bison 3.x
 592
 593  * Internal APIs
 594     - Added ast.h to exported headers
 595     - Added ScriptPass helper class for script-like passes
 596     - Added CellEdgesDatabase API
 597
 598  * Front-ends and Back-ends
 599     - Added filename glob support to all front-ends
 600     - Added avail (black-box) module params to ilang format
 601     - Added $display %m support
 602     - Added support for $stop Verilog system task
 603     - Added support for SystemVerilog packages
 604     - Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b}
 605     - Added support for "active high" and "active low" latches in read_blif and write_blif
 606     - Use init value "2" for all uninitialized FFs in BLIF back-end
 607     - Added "read_blif -sop"
 608     - Added "write_blif -noalias"
 609     - Added various write_blif options for VTR support
 610     - write_json: also write module attributes.
 611     - Added "write_verilog -nodec -nostr -defparam"
 612     - Added "read_verilog -norestrict -assume-asserts"
 613     - Added support for bus interfaces to "read_liberty -lib"
 614     - Added liberty parser support for types within cell decls
 615     - Added "write_verilog -renameprefix -v"
 616     - Added "write_edif -nogndvcc"
 617
 618  * Formal Verification
 619     - Support for hierarchical designs in smt2 back-end
 620     - Yosys-smtbmc: Support for hierarchical VCD dumping
 621     - Added $initstate cell type and vlog function
 622     - Added $anyconst and $anyseq cell types and vlog functions
 623     - Added printing of code loc of failed asserts to yosys-smtbmc
 624     - Added memory_memx pass, "memory -memx", and "prep -memx"
 625     - Added "proc_mux -ifx"
 626     - Added "yosys-smtbmc -g"
 627     - Deprecated "write_smt2 -regs" (by default on now)
 628     - Made "write_smt2 -bv -mem" default, added "write_smt2 -nobv -nomem"
 629     - Added support for memories to smtio.py
 630     - Added "yosys-smtbmc --dump-vlogtb"
 631     - Added "yosys-smtbmc --smtc --dump-smtc"
 632     - Added "yosys-smtbmc --dump-all"
 633     - Added assertpmux command
 634     - Added "yosys-smtbmc --unroll"
 635     - Added $past, $stable, $rose, $fell SVA functions
 636     - Added "yosys-smtbmc --noinfo and --dummy"
 637     - Added "yosys-smtbmc --noincr"
 638     - Added "yosys-smtbmc --cex <filename>"
 639     - Added $ff and $_FF_ cell types
 640     - Added $global_clock verilog syntax support for creating $ff cells
 641     - Added clk2fflogic
 642
 643
 644 Yosys 0.5 .. Yosys 0.6
 645 ----------------------
 646
 647  * Various
 648      - Added Contributor Covenant Code of Conduct
 649      - Various improvements in dict<> and pool<>
 650      - Added hashlib::mfp and refactored SigMap
 651      - Improved support for reals as module parameters
 652      - Various improvements in SMT2 back-end
 653      - Added "keep_hierarchy" attribute
 654      - Verilog front-end: define `BLACKBOX in -lib mode
 655      - Added API for converting internal cells to AIGs
 656      - Added ENABLE_LIBYOSYS Makefile option
 657      - Removed "techmap -share_map" (use "-map +/filename" instead)
 658      - Switched all Python scripts to Python 3
 659      - Added support for $display()/$write() and $finish() to Verilog front-end
 660      - Added "yosys-smtbmc" formal verification flow
 661      - Added options for clang sanitizers to Makefile
 662
 663  * New commands and options
 664      - Added "scc -expect <N> -nofeedback"
 665      - Added "proc_dlatch"
 666      - Added "check"
 667      - Added "select %xe %cie %coe %M %C %R"
 668      - Added "sat -dump_json" (WaveJSON format)
 669      - Added "sat -tempinduct-baseonly -tempinduct-inductonly"
 670      - Added "sat -stepsize" and "sat -tempinduct-step"
 671      - Added "sat -show-regs -show-public -show-all"
 672      - Added "write_json" (Native Yosys JSON format)
 673      - Added "write_blif -attr"
 674      - Added "dffinit"
 675      - Added "chparam"
 676      - Added "muxcover"
 677      - Added "pmuxtree"
 678      - Added memory_bram "make_outreg" feature
 679      - Added "splice -wires"
 680      - Added "dff2dffe -direct-match"
 681      - Added simplemap $lut support
 682      - Added "read_blif"
 683      - Added "opt_share -share_all"
 684      - Added "aigmap"
 685      - Added "write_smt2 -mem -regs -wires"
 686      - Added "memory -nordff"
 687      - Added "write_smv"
 688      - Added "synth -nordff -noalumacc"
 689      - Added "rename -top new_name"
 690      - Added "opt_const -clkinv"
 691      - Added "synth -nofsm"
 692      - Added "miter -assert"
 693      - Added "read_verilog -noautowire"
 694      - Added "read_verilog -nodpi"
 695      - Added "tribuf"
 696      - Added "lut2mux"
 697      - Added "nlutmap"
 698      - Added "qwp"
 699      - Added "test_cell -noeval"
 700      - Added "edgetypes"
 701      - Added "equiv_struct"
 702      - Added "equiv_purge"
 703      - Added "equiv_mark"
 704      - Added "equiv_add -try -cell"
 705      - Added "singleton"
 706      - Added "abc -g -luts"
 707      - Added "torder"
 708      - Added "write_blif -cname"
 709      - Added "submod -copy"
 710      - Added "dffsr2dff"
 711      - Added "stat -liberty"
 712
 713  * Synthesis metacommands
 714      - Various improvements in synth_xilinx
 715      - Added synth_ice40 and synth_greenpak4
 716      - Added "prep" metacommand for "synthesis lite"
 717
 718  * Cell library changes
 719      - Added cell types to "help" system
 720      - Added $meminit cell type
 721      - Added $assume cell type
 722      - Added $_MUX4_, $_MUX8_, and $_MUX16_ cells
 723      - Added $tribuf and $_TBUF_ cell types
 724      - Added read-enable to memory model
 725
 726  * YosysJS
 727      - Various improvements in emscripten build
 728      - Added alternative webworker-based JS API
 729      - Added a few example applications
 730
 731
 732 Yosys 0.4 .. Yosys 0.5
 733 ----------------------
 734
 735  * API changes
 736      - Added log_warning()
 737      - Added eval_select_args() and eval_select_op()
 738      - Added cell->known(), cell->input(portname), cell->output(portname)
 739      - Skip blackbox modules in design->selected_modules()
 740      - Replaced std::map<> and std::set<> with dict<> and pool<>
 741      - New SigSpec::extend() is what used to be SigSpec::extend_u0()
 742      - Added YS_OVERRIDE, YS_FINAL, YS_ATTRIBUTE, YS_NORETURN
 743
 744  * Cell library changes
 745      - Added flip-flops with enable ($dffe etc.)
 746      - Added $equiv cells for equivalence checking framework
 747
 748  * Various
 749      - Updated ABC to hg rev 61ad5f908c03
 750      - Added clock domain partitioning to ABC pass
 751      - Improved plugin building (see "yosys-config --build")
 752      - Added ENABLE_NDEBUG Makefile flag for high-performance builds
 753      - Added "yosys -d", "yosys -L" and other driver improvements
 754      - Added support for multi-bit (array) cell ports to "write_edif"
 755      - Now printing most output to stdout, not stderr
 756      - Added "onehot" attribute (set by "fsm_map")
 757      - Various performance improvements
 758      - Vastly improved Xilinx flow
 759      - Added "make unsintall"
 760
 761  * Equivalence checking
 762      - Added equivalence checking commands:
 763          equiv_make equiv_simple equiv_status
 764          equiv_induct equiv_miter
 765          equiv_add equiv_remove
 766
 767  * Block RAM support:
 768      - Added "memory_bram" command
 769      - Added BRAM support to Xilinx flow
 770
 771  * Other New Commands and Options
 772      - Added "dff2dffe"
 773      - Added "fsm -encfile"
 774      - Added "dfflibmap -prepare"
 775      - Added "write_blid -unbuf -undef -blackbox"
 776      - Added "write_smt2" for writing SMT-LIBv2 files
 777      - Added "test_cell -w -muxdiv"
 778      - Added "select -read"
 779
 780
 781 Yosys 0.3.0 .. Yosys 0.4
 782 ------------------------
 783
 784  * Platform Support
 785      - Added support for mxe-based cross-builds for win32
 786      - Added sourcecode-export as VisualStudio project
 787      - Added experimental EMCC (JavaScript) support
 788
 789  * Verilog Frontend
 790      - Added -sv option for SystemVerilog (and automatic *.sv file support)
 791      - Added support for real-valued constants and constant expressions
 792      - Added support for non-standard "via_celltype" attribute on task/func
 793      - Added support for non-standard "module mod_name(...);" syntax
 794      - Added support for non-standard """ macro bodies
 795      - Added support for array with more than one dimension
 796      - Added support for $readmemh and $readmemb
 797      - Added support for DPI functions
 798
 799  * Changes in internal cell library
 800      - Added $shift and $shiftx cell types
 801      - Added $alu, $lcu, $fa and $macc cell types
 802      - Removed $bu0 and $safe_pmux cell types
 803      - $mem/$memwr WR_EN input is now a per-data-bit enable signal
 804      - Added $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
 805      - Renamed ports of $lut cells (from I->O to A->Y)
 806      - Renamed $_INV_ to $_NOT_
 807
 808  * Changes for simple synthesis flows
 809      - There is now a "synth" command with a recommended default script
 810      - Many improvements in synthesis of arithmetic functions to gates
 811          - Multipliers and adders with many operands are using carry-save adder trees
 812          - Remaining adders are now implemented using Brent-Kung carry look-ahead adders
 813      - Various new high-level optimizations on RTL netlist
 814      - Various improvements in FSM optimization
 815      - Updated ABC to hg 5b5af75f1dda (from 2014-11-07)
 816
 817  * Changes in internal APIs and RTLIL
 818      - Added log_id() and log_cell() helper functions
 819      - Added function-like cell creation helpers
 820      - Added GetSize() function (like .size() but with int)
 821      - Major refactoring of RTLIL::Module and related classes
 822      - Major refactoring of RTLIL::SigSpec and related classes
 823      - Now RTLIL::IdString is essentially an int
 824      - Added macros for code coverage counters
 825      - Added some Makefile magic for pretty make logs
 826      - Added "kernel/yosys.h" with all the core definitions
 827      - Changed a lot of code from FILE* to c++ streams
 828      - Added RTLIL::Monitor API and "trace" command
 829      - Added "Yosys" C++ namespace
 830
 831  * Changes relevant to SAT solving
 832      - Added ezSAT::keep_cnf() and ezSAT::non_incremental()
 833      - Added native ezSAT support for vector shift ops
 834      - Updated MiniSAT to git 37dc6c67e2 (from 2013-09-25)
 835
 836  * New commands (or large improvements to commands)
 837      - Added "synth" command with default script
 838      - Added "share" (finally some real resource sharing)
 839      - Added "memory_share" (reduce number of ports on memories)
 840      - Added "wreduce" and "alumacc" commands
 841      - Added "opt -keepdc -fine -full -fast"
 842      - Added some "test_*" commands
 843
 844  * Various other changes
 845      - Added %D and %c select operators
 846      - Added support for labels in yosys scripts
 847      - Added support for here-documents in yosys scripts
 848      - Support "+/" prefix for files from proc_share_dir
 849      - Added "autoidx" statement to ilang language
 850      - Switched from "yosys-svgviewer" to "xdot"
 851      - Renamed "stdcells.v" to "techmap.v"
 852      - Various bug fixes and small improvements
 853      - Improved welcome and bye messages
 854
 855
 856 Yosys 0.2.0 .. Yosys 0.3.0
 857 --------------------------
 858
 859  * Driver program and overall behavior:
 860      - Added "design -push" and "design -pop"
 861      - Added "tee" command for redirecting log output
 862
 863  * Changes in the internal cell library:
 864      - Added $dlatchsr and $_DLATCHSR_???_ cell types
 865
 866  * Improvements in Verilog frontend:
 867      - Improved support for const functions (case, always, repeat)
 868      - The generate..endgenerate keywords are now optional
 869      - Added support for arrays of module instances
 870      - Added support for "`default_nettype" directive
 871      - Added support for "`line" directive
 872
 873  * Other front- and back-ends:
 874      - Various changes to "write_blif" options
 875      - Various improvements in EDIF backend
 876      - Added "vhdl2verilog" pseudo-front-end
 877      - Added "verific" pseudo-front-end
 878
 879  * Improvements in technology mapping:
 880      - Added support for recursive techmap
 881      - Added CONSTMSK and CONSTVAL features to techmap
 882      - Added _TECHMAP_CONNMAP_*_ feature to techmap
 883      - Added _TECHMAP_REPLACE_ feature to techmap
 884      - Added "connwrappers" command for wrap-extract-unwrap method
 885      - Added "extract -map %<design_name>" feature
 886      - Added "extract -ignore_param ..." and "extract -ignore_parameters"
 887      - Added "techmap -max_iter" option
 888
 889  * Improvements to "eval" and "sat" framework:
 890      - Now include a copy of Minisat (with build fixes applied)
 891      - Switched to Minisat::SimpSolver as SAT back-end
 892      - Added "sat -dump_vcd" feature
 893      - Added "sat -dump_cnf" feature
 894      - Added "sat -initsteps <N>" feature
 895      - Added "freduce -stop <N>" feature
 896      - Added "freduce -dump <prefix>" feature
 897
 898  * Integration with ABC:
 899      - Updated ABC rev to 7600ffb9340c
 900
 901  * Improvements in the internal APIs:
 902      - Added RTLIL::Module::add... helper methods
 903      - Various build fixes for OSX (Darwin) and OpenBSD
 904
 905
 906 Yosys 0.1.0 .. Yosys 0.2.0
 907 --------------------------
 908
 909  * Changes to the driver program:
 910      - Added "yosys -h" and "yosys -H"
 911      - Added support for backslash line continuation in scripts
 912      - Added support for #-comments in same line as command
 913      - Added "echo" and "log" commands
 914
 915  * Improvements in Verilog frontend:
 916      - Added support for local registers in named blocks
 917      - Added support for "case" in "generate" blocks
 918      - Added support for $clog2 system function
 919      - Added support for basic SystemVerilog assert statements
 920      - Added preprocessor support for macro arguments
 921      - Added preprocessor support for `elsif statement
 922      - Added "verilog_defaults" command
 923      - Added read_verilog -icells option
 924      - Added support for constant sizes from parameters
 925      - Added "read_verilog -setattr"
 926      - Added support for function returning 'integer'
 927      - Added limited support for function calls in parameter values
 928      - Added "read_verilog -defer" to suppress evaluation of modules with default parameters
 929
 930  * Other front- and back-ends:
 931      - Added BTOR backend
 932      - Added Liberty frontend
 933
 934  * Improvements in technology mapping:
 935      - The "dfflibmap" command now strongly prefers solutions with
 936            no inverters in clock paths
 937      - The "dfflibmap" command now prefers cells with smaller area
 938      - Added support for multiple -map options to techmap
 939      - Added "dfflibmap" support for //-comments in liberty files
 940      - Added "memory_unpack" command to revert "memory_collect"
 941      - Added standard techmap rule "techmap -share_map pmux2mux.v"
 942      - Added "iopadmap -bits"
 943      - Added "setundef" command
 944      - Added "hilomap" command
 945
 946  * Changes in the internal cell library:
 947      - Major rewrite of simlib.v for better compatibility with other tools
 948      - Added PRIORITY parameter to $memwr cells
 949      - Added TRANSPARENT parameter to $memrd cells
 950      - Added RD_TRANSPARENT parameter to $mem cells
 951      - Added $bu0 cell (always 0-extend, even undef MSB)
 952      - Added $assert cell type
 953      - Added $slice and $concat cell types
 954
 955  * Integration with ABC:
 956      - Updated ABC to hg rev 2058c8ccea68
 957      - Tighter integration of ABC build with Yosys build. The make
 958            targets 'make abc' and 'make install-abc' are now obsolete.
 959      - Added support for passing FFs from one clock domain through ABC
 960      - Now always use BLIF as exchange format with ABC
 961      - Added support for "abc -script +<command_sequence>"
 962      - Improved standard ABC recipe
 963      - Added support for "keep" attribute to abc command
 964      - Added "abc -dff / -clk / -keepff" options
 965
 966  * Improvements to "eval" and "sat" framework:
 967      - Added support for "0" and "~0" in right-hand side -set expressions
 968      - Added "eval -set-undef" and "eval -table"
 969      - Added "sat -set-init" and "sat -set-init-*" for sequential problems
 970      - Added undef support to SAT solver, incl. various new "sat" options
 971      - Added correct support for === and !== for "eval" and "sat"
 972      - Added "sat -tempinduct" (default -seq is now non-induction sequential)
 973      - Added "sat -prove-asserts"
 974      - Complete rewrite of the 'freduce' command
 975      - Added "miter" command
 976      - Added "sat -show-inputs" and "sat -show-outputs"
 977      - Added "sat -ignore_unknown_cells" (now produce an error by default)
 978      - Added "sat -falsify"
 979      - Now "sat -verify" and "sat -falsify" can also be used without "-prove"
 980      - Added "expose" command
 981      - Added support for @<sel_name> to sat and eval signal expressions
 982
 983  * Changes in the 'make test' framework and auxiliary test tools:
 984      - Added autotest.sh -p and -f options
 985      - Replaced autotest.sh ISIM support with XSIM support
 986      - Added test cases for SAT framework
 987
 988  * Added "abbreviated IDs":
 989      - Now $<something>$foo can be abbreviated as $foo.
 990      - Usually this last part is a unique id (from RTLIL::autoidx)
 991      - This abbreviated IDs are now also used in "show" output
 992
 993  * Other changes to selection framework:
 994      - Now */ is optional in */<mode>:<arg> expressions
 995      - Added "select -assert-none" and "select -assert-any"
 996      - Added support for matching modules by attribute (A:<expr>)
 997      - Added "select -none"
 998      - Added support for r:<expr> pattern for matching cell parameters
 999      - Added support for !=, <, <=, >=, > for attribute and parameter matching
1000      - Added support for %s for selecting sub-modules
1001      - Added support for %m for expanding selections to whole modules
1002      - Added support for i:*, o:* and x:* pattern for selecting module ports
1003      - Added support for s:<expr> pattern for matching wire width
1004      - Added support for %a operation to select wire aliases
1005
1006  * Various other changes to commands and options:
1007      - The "ls" command now supports wildcards
1008      - Added "show -pause" and "show -format dot"
1009      - Added "show -color" support for cells
1010      - Added "show -label" and "show -notitle"
1011      - Added "dump -m" and "dump -n"
1012      - Added "history" command
1013      - Added "rename -hide"
1014      - Added "connect" command
1015      - Added "splitnets -driver"
1016      - Added "opt_const -mux_undef"
1017      - Added "opt_const -mux_bool"
1018      - Added "opt_const -undriven"
1019      - Added "opt -mux_undef -mux_bool -undriven -purge"
1020      - Added "hierarchy -libdir"
1021      - Added "hierarchy -purge_lib" (by default now do not remove lib cells)
1022      - Added "delete" command
1023      - Added "dump -append"
1024      - Added "setattr" and "setparam" commands
1025      - Added "design -stash/-copy-from/-copy-to"
1026      - Added "copy" command
1027      - Added "splice" command
1028