CHANGELOG

   1
   2 List of major changes and improvements between releases
   3 =======================================================
   4
   5 Yosys 0.16 .. Yosys 0.16-dev
   6 --------------------------
   7
   8  * SystemVerilog
   9     - Fixed automatic `nosync` inference for local variables in `always_comb`
  10       procedures not applying to nested blocks and blocks in functions
  11
  12 Yosys 0.15 .. Yosys 0.16
  13 --------------------------
  14  * Various
  15     - Added BTOR2 witness file co-simulation.
  16     - Simulation calls external vcd2fst for VCD conversion.
  17     - Added fst2tb pass - generates testbench for the circuit using
  18       the given top-level module and simulus signal from FST file.
  19     - yosys-smtbmc: Option to keep going after failed assertions in BMC mode
  20
  21  * Verific support
  22     - Import modules in alphabetic (reproducable) order.
  23
  24 Yosys 0.14 .. Yosys 0.15
  25 --------------------------
  26
  27  * Various
  28     - clk2fflogic: nice names for autogenerated signals
  29     - simulation include support for all flip-flop types.
  30     - Added AIGER witness file co-simulation.
  31
  32  * Verilog
  33     - Fixed evaluation of constant functions with variables or arguments with
  34       reversed dimensions
  35     - Fixed elaboration of dynamic range assignments where the vector is
  36       reversed or is not zero-indexed
  37     - Added frontend support for time scale delay values (e.g., `#1ns`)
  38
  39  * SystemVerilog
  40     - Added support for accessing whole sub-structures in expressions
  41
  42  * New commands and options
  43     - Added glift command, used to create gate-level information flow tracking
  44       (GLIFT) models by the "constructive mapping" approach
  45
  46  * Verific support
  47     - Ability to override default parser mode for verific -f command.
  48
  49 Yosys 0.13 .. Yosys 0.14
  50 --------------------------
  51
  52  * Various
  53     - Added $bmux and $demux cells and related optimization patterns.
  54
  55  * New commands and options
  56     - Added "bmuxmap" and "dmuxmap" passes
  57     - Added "-fst" option to "sim" pass for writing FST files
  58     - Added "-r", "-scope", "-start", "-stop", "-at", "-sim", "-sim-gate",
  59       "-sim-gold" options to "sim" pass for co-simulation
  60
  61  * Anlogic support
  62     - Added support for BRAMs
  63
  64 Yosys 0.12 .. Yosys 0.13
  65 --------------------------
  66
  67  * Various
  68     - Use "read" command to parse HDL files from Yosys command-line
  69     - Added "yosys -r <topmodule>" command line option
  70     - write_verilog: dump zero width sigspecs correctly
  71
  72  * SystemVerilog
  73     - Fixed regression preventing the use array querying functions in case
  74       expressions and case item expressions
  75     - Fixed static size casts inadvertently limiting the result width of binary
  76       operations
  77     - Fixed static size casts ignoring expression signedness
  78     - Fixed static size casts not extending unbased unsized literals
  79     - Added automatic `nosync` inference for local variables in `always_comb`
  80       procedures which are always assigned before they are used to avoid errant
  81       latch inference
  82
  83  * New commands and options
  84     - Added "clean_zerowidth" pass
  85
  86  * Verific support
  87     - Add YOSYS to the implicitly defined verilog macros in verific
  88
  89 Yosys 0.11 .. Yosys 0.12
  90 --------------------------
  91
  92  * Various
  93     - Added iopadmap native support for negative-polarity output enable
  94     - ABC update
  95
  96  * SystemVerilog
  97     - Support parameters using struct as a wiretype
  98
  99  * New commands and options
 100     - Added "-genlib" option to "abc" pass
 101     - Added "sta" very crude static timing analysis pass
 102
 103  * Verific support
 104     - Fixed memory block size in import
 105
 106  * New back-ends
 107     - Added support for GateMate FPGA from Cologne Chip AG
 108
 109  * Intel ALM support
 110     - Added preliminary Arria V support
 111
 112
 113 Yosys 0.10 .. Yosys 0.11
 114 --------------------------
 115
 116  * Various
 117     - Added $aldff and $aldffe (flip-flops with async load) cells
 118
 119  * SystemVerilog
 120     - Fixed an issue which prevented writing directly to a memory word via a
 121       connection to an output port
 122     - Fixed an issue which prevented unbased unsized literals (e.g., `'1`) from
 123       filling the width of a cell input
 124     - Fixed an issue where connecting a slice covering the entirety of a signed
 125       signal to a cell input would cause a failed assertion
 126
 127  * Verific support
 128     - Importer support for {PRIM,WIDE_OPER}_DFF
 129     - Importer support for PRIM_BUFIF1
 130     - Option to use Verific without VHDL support
 131     - Importer support for {PRIM,WIDE_OPER}_DLATCH{,RS}
 132     - Added -cfg option for getting/setting Verific runtime flags
 133
 134 Yosys 0.9 .. Yosys 0.10
 135 --------------------------
 136
 137  * Various
 138     - Added automatic gzip decompression for frontends
 139     - Added $_NMUX_ cell type
 140     - Added automatic gzip compression (based on filename extension) for backends
 141     - Improve attribute and parameter encoding in JSON to avoid ambiguities between
 142       bit vectors and strings containing [01xz]*
 143     - Improvements in pmgen: subpattern and recursive matches
 144     - Support explicit FIRRTL properties
 145     - Improvements in pmgen: slices, choices, define, generate
 146     - Added "_TECHMAP_WIREINIT_*_" parameter and "_TECHMAP_REMOVEINIT_*_" wire for "techmap" pass
 147     - Added +/mul2dsp.v for decomposing wide multipliers to custom-sized ones
 148     - Added new frontend: rpc
 149     - Added --version and -version as aliases for -V
 150     - Improve yosys-smtbmc "solver not found" handling
 151     - Improved support of $readmem[hb] Memory Content File inclusion
 152     - Added CXXRTL backend
 153     - Use YosysHQ/abc instead of upstream berkeley-abc/abc
 154     - Added WASI platform support.
 155     - Added extmodule support to firrtl backend
 156     - Added $divfloor and $modfloor cells
 157     - Added $adffe, $dffsre, $sdff, $sdffe, $sdffce, $adlatch cells
 158     - Added "_TECHMAP_CELLNAME_" parameter for "techmap" pass
 159     - Added firrtl backend support for generic parameters in blackbox components
 160     - Added $meminit_v2 cells (with support for write mask)
 161     - Added $mem_v2, $memrd_v2, $memwr_v2, with the following features:
 162       - write priority masks, per write/write port pair
 163       - transparency and undefined collision behavior masks, per read/write port pair
 164       - read port reset and initialization
 165       - wide ports (accessing a naturally aligned power-of-two number of memory cells)
 166
 167  * New commands and options
 168     - Added "write_xaiger" backend
 169     - Added "read_xaiger"
 170     - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only)
 171     - Added "synth -abc9" (experimental)
 172     - Added "script -scriptwire"
 173     - Added "clkbufmap" pass
 174     - Added "extractinv" pass and "invertible_pin" attribute
 175     - Added "proc_clean -quiet"
 176     - Added "proc_prune" pass
 177     - Added "stat -tech cmos"
 178     - Added "opt_share" pass, run as part of "opt -full"
 179     - Added "-match-init" option to "dff2dffs" pass
 180     - Added "equiv_opt -multiclock"
 181     - Added "techmap_autopurge" support to techmap
 182     - Added "add -mod <modname[s]>"
 183     - Added "paramap" pass
 184     - Added "portlist" command
 185     - Added "check -mapped"
 186     - Added "check -allow-tbuf"
 187     - Added "autoname" pass
 188     - Added "write_verilog -extmem"
 189     - Added "opt_mem" pass
 190     - Added "scratchpad" pass
 191     - Added "fminit" pass
 192     - Added "opt_lut_ins" pass
 193     - Added "logger" pass
 194     - Added "show -nobg"
 195     - Added "exec" command
 196     - Added "design -delete"
 197     - Added "design -push-copy"
 198     - Added "qbfsat" command
 199     - Added "select -unset"
 200     - Added "dfflegalize" pass
 201     - Removed "opt_expr -clkinv" option, made it the default
 202     - Added "proc -nomux
 203     - Merged "dffsr2dff", "opt_rmdff", "dff2dffe", "dff2dffs", "peepopt.dffmux" passes into a new "opt_dff" pass
 204
 205  * SystemVerilog
 206     - Added checking of always block types (always_comb, always_latch and always_ff)
 207     - Added support for wildcard port connections (.*)
 208     - Added support for enum typedefs
 209     - Added support for structs and packed unions.
 210     - Allow constant function calls in for loops and generate if and case
 211     - Added support for static cast
 212     - Added support for logic typed parameters
 213     - Fixed generate scoping issues
 214     - Added support for real-valued parameters
 215     - Allow localparams in constant functions
 216     - Module name scope support
 217     - Support recursive functions using ternary expressions
 218     - Extended support for integer types
 219     - Support for parameters without default values
 220     - Allow globals in one file to depend on globals in another
 221     - Added support for: *=, /=, %=, <<=, >>=, <<<=, >>>=
 222     - Added support for parsing the 'bind' construct
 223     - support declaration in procedural for initialization
 224     - support declaration in generate for initialization
 225     - Support wand and wor of data types
 226
 227  * Verific support
 228     - Added "verific -L"
 229     - Add Verific SVA support for "always" properties
 230     - Add Verific support for SVA nexttime properties
 231     - Improve handling of verific primitives in "verific -import -V" mode
 232     - Import attributes for wires
 233     - Support VHDL enums
 234     - Added support for command files
 235
 236  * New back-ends
 237     - Added initial EFINIX support
 238     - Added Intel ALM: alternative synthesis for Intel FPGAs
 239     - Added initial Nexus support
 240     - Added initial MachXO2 support
 241     - Added initial QuickLogic PolarPro 3 support
 242
 243  * ECP5 support
 244     - Renamed labels/options in synth_ecp5 (e.g. dram -> map_lutram; -nodram -> -nolutram)
 245     - Added "synth_ecp5 -abc9" (experimental)
 246     - Added "synth_ecp5 -nowidelut"
 247     - "synth_ecp5" to now infer DSP blocks (-nodsp to disable, experimental)
 248
 249  * iCE40 support
 250     - Added "synth_ice40 -abc9" (experimental)
 251     - Added "synth_ice40 -device"
 252     - Renamed labels/options in synth_ice40 (e.g. dram -> map_lutram; -nodram -> -nolutram)
 253     - Added "ice40_wrapcarry" to encapsulate SB_LUT+SB_CARRY pairs for techmapping
 254     - Removed "ice40_unlut"
 255     - Added "ice40_dsp" for Lattice iCE40 DSP packing
 256     - "synth_ice40 -dsp" to infer DSP blocks
 257
 258  * Xilinx support
 259     - Added "synth_xilinx -abc9" (experimental)
 260     - Added "synth_xilinx -nocarry"
 261     - Added "synth_xilinx -nowidelut"
 262     - "synth_xilinx" to now infer wide multiplexers (-widemux <min> to enable)
 263     - Renamed labels/options in synth_xilinx (e.g. dram -> map_lutram; -nodram -> -nolutram)
 264     - Added "synth_xilinx -family xc6s" for Spartan 6 support (experimental)
 265     - Added "synth_xilinx -ise" (experimental)
 266     - Added "synth_xilinx -iopad"
 267     - "synth_xilinx" now automatically inserts clock buffers (add -noclkbuf to disable)
 268     - Added "xilinx_srl" for Xilinx shift register extraction
 269     - Removed "shregmap -tech xilinx" (superseded by "xilinx_srl")
 270     - Added "xilinx_dsp" for Xilinx DSP packing
 271     - "synth_xilinx" to now infer DSP blocks (-nodsp to disable)
 272     - Added latch support to synth_xilinx
 273     - Added support for flip-flops with synchronous reset to synth_xilinx
 274     - Added support for flip-flops with reset and enable to synth_xilinx
 275     - Added "xilinx_dffopt" pass
 276     - Added "synth_xilinx -dff"
 277
 278  * Intel support
 279     - Renamed labels in synth_intel (e.g. bram -> map_bram)
 280     - synth_intel: cyclone10 -> cyclone10lp, a10gx -> arria10gx
 281     - Added "intel_alm -abc9" (experimental)
 282
 283  * CoolRunner2 support
 284     - Separate and improve buffer cell insertion pass
 285     - Use extract_counter to optimize counters
 286
 287 Yosys 0.8 .. Yosys 0.9
 288 ----------------------
 289
 290  * Various
 291     - Many bugfixes and small improvements
 292     - Added support for SystemVerilog interfaces and modports
 293     - Added "write_edif -attrprop"
 294     - Added "opt_lut" pass
 295     - Added "gate2lut.v" techmap rule
 296     - Added "rename -src"
 297     - Added "equiv_opt" pass
 298     - Added "flowmap" LUT mapping pass
 299     - Added "rename -wire" to rename cells based on the wires they drive
 300     - Added "bugpoint" for creating minimised testcases
 301     - Added "write_edif -gndvccy"
 302     - "write_verilog" to escape Verilog keywords
 303     - Fixed sign handling of real constants
 304     - "write_verilog" to write initial statement for initial flop state
 305     - Added pmgen pattern matcher generator
 306     - Fixed opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_
 307     - Added "setundef -params" to replace undefined cell parameters
 308     - Renamed "yosys -D" to "yosys -U", added "yosys -D" to set Verilog defines
 309     - Fixed handling of defparam when default_nettype is none
 310     - Fixed "wreduce" flipflop handling
 311     - Fixed FIRRTL to Verilog process instance subfield assignment
 312     - Added "write_verilog -siminit"
 313     - Several fixes and improvements for mem2reg memories
 314     - Fixed handling of task output ports in clocked always blocks
 315     - Improved handling of and-with-1 and or-with-0 in "opt_expr"
 316     - Added "read_aiger" frontend
 317     - Added "mutate" pass
 318     - Added "hdlname" attribute
 319     - Added "rename -output"
 320     - Added "read_ilang -lib"
 321     - Improved "proc" full_case detection and handling
 322     - Added "whitebox" and "lib_whitebox" attributes
 323     - Added "read_verilog -nowb", "flatten -wb" and "wbflip"
 324     - Added Python bindings and support for Python plug-ins
 325     - Added "pmux2shiftx"
 326     - Added log_debug framework for reduced default verbosity
 327     - Improved "opt_expr" and "opt_clean" handling of (partially) undriven and/or unused wires
 328     - Added "peepopt" peephole optimisation pass using pmgen
 329     - Added approximate support for SystemVerilog "var" keyword
 330     - Added parsing of "specify" blocks into $specrule and $specify[23]
 331     - Added support for attributes on parameters and localparams
 332     - Added support for parsing attributes on port connections
 333     - Added "wreduce -keepdc"
 334     - Added support for optimising $dffe and $_DFFE_* cells in "opt_rmdff"
 335     - Added Verilog wand/wor wire type support
 336     - Added support for elaboration system tasks
 337     - Added "muxcover -mux{4,8,16}=<cost>"
 338     - Added "muxcover -dmux=<cost>"
 339     - Added "muxcover -nopartial"
 340     - Added "muxpack" pass
 341     - Added "pmux2shiftx -norange"
 342     - Added support for "~" in filename parsing
 343     - Added "read_verilog -pwires" feature to turn parameters into wires
 344     - Fixed sign extension of unsized constants with 'bx and 'bz MSB
 345     - Fixed genvar to be a signed type
 346     - Added support for attributes on case rules
 347     - Added "upto" and "offset" to JSON frontend and backend
 348     - Several liberty file parser improvements
 349     - Fixed handling of more complex BRAM patterns
 350     - Add "write_aiger -I -O -B"
 351
 352  * Formal Verification
 353     - Added $changed support to read_verilog
 354     - Added "read_verilog -noassert -noassume -assert-assumes"
 355     - Added btor ops for $mul, $div, $mod and $concat
 356     - Added yosys-smtbmc support for btor witnesses
 357     - Added "supercover" pass
 358     - Fixed $global_clock handling vs autowire
 359     - Added $dffsr support to "async2sync"
 360     - Added "fmcombine" pass
 361     - Added memory init support in "write_btor"
 362     - Added "cutpoint" pass
 363     - Changed "ne" to "neq" in btor2 output
 364     - Added support for SVA "final" keyword
 365     - Added "fmcombine -initeq -anyeq"
 366     - Added timescale and generated-by header to yosys-smtbmc vcd output
 367     - Improved BTOR2 handling of undriven wires
 368
 369  * Verific support
 370     - Enabled Verific flags vhdl_support_variable_slice and veri_elaborate_top_level_modules_having_interface_ports
 371     - Improved support for asymmetric memories
 372     - Added "verific -chparam"
 373     - Fixed "verific -extnets" for more complex situations
 374     - Added "read -verific" and "read -noverific"
 375     - Added "hierarchy -chparam"
 376
 377  * New back-ends
 378     - Added initial Anlogic support
 379     - Added initial SmartFusion2 and IGLOO2 support
 380
 381  * ECP5 support
 382     - Added "synth_ecp5 -nowidelut"
 383     - Added BRAM inference support to "synth_ecp5"
 384     - Added support for transforming Diamond IO and flipflop primitives
 385
 386  * iCE40 support
 387     - Added "ice40_unlut" pass
 388     - Added "synth_ice40 -relut"
 389     - Added "synth_ice40 -noabc"
 390     - Added "synth_ice40 -dffe_min_ce_use"
 391     - Added DSP inference support using pmgen
 392     - Added support for initialising BRAM primitives from a file
 393     - Added iCE40 Ultra RGB LED driver cells
 394
 395  * Xilinx support
 396     - Use "write_edif -pvector bra" for Xilinx EDIF files
 397     - Fixes for VPR place and route support with "synth_xilinx"
 398     - Added more cell simulation models
 399     - Added "synth_xilinx -family"
 400     - Added "stat -tech xilinx" to estimate logic cell usage
 401     - Added "synth_xilinx -nocarry"
 402     - Added "synth_xilinx -nowidelut"
 403     - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
 404     - Added support for mapping RAM32X1D
 405
 406 Yosys 0.7 .. Yosys 0.8
 407 ----------------------
 408
 409  * Various
 410     - Many bugfixes and small improvements
 411     - Strip debug symbols from installed binary
 412     - Replace -ignore_redef with -[no]overwrite in front-ends
 413     - Added write_verilog hex dump support, add -nohex option
 414     - Added "write_verilog -decimal"
 415     - Added "scc -set_attr"
 416     - Added "verilog_defines" command
 417     - Remember defines from one read_verilog to next
 418     - Added support for hierarchical defparam
 419     - Added FIRRTL back-end
 420     - Improved ABC default scripts
 421     - Added "design -reset-vlog"
 422     - Added "yosys -W regex", "yosys -w regex", and "yosys -e regex"
 423     - Added Verilog $rtoi and $itor support
 424     - Added "check -initdrv"
 425     - Added "read_blif -wideports"
 426     - Added support for SystemVerilog "++" and "--" operators
 427     - Added support for SystemVerilog unique, unique0, and priority case
 428     - Added "write_edif" options for edif "flavors"
 429     - Added support for resetall compiler directive
 430     - Added simple C beck-end (bitwise combinatorical only atm)
 431     - Added $_ANDNOT_ and $_ORNOT_ cell types
 432     - Added cell library aliases to "abc -g"
 433     - Added "setundef -anyseq"
 434     - Added "chtype" command
 435     - Added "design -import"
 436     - Added "write_table" command
 437     - Added "read_json" command
 438     - Added "sim" command
 439     - Added "extract_fa" and "extract_reduce" commands
 440     - Added "extract_counter" command
 441     - Added "opt_demorgan" command
 442     - Added support for $size and $bits SystemVerilog functions
 443     - Added "blackbox" command
 444     - Added "ltp" command
 445     - Added support for editline as replacement for readline
 446     - Added warnings for driver-driver conflicts between FFs (and other cells) and constants
 447     - Added "yosys -E" for creating Makefile dependencies files
 448     - Added "synth -noshare"
 449     - Added "memory_nordff"
 450     - Added "setundef -undef -expose -anyconst"
 451     - Added "expose -input"
 452     - Added specify/specparam parser support (simply ignore them)
 453     - Added "write_blif -inames -iattr"
 454     - Added "hierarchy -simcheck"
 455     - Added an option to statically link abc into yosys
 456     - Added protobuf back-end
 457     - Added BLIF parsing support for .conn and .cname
 458     - Added read_verilog error checking for reg/wire/logic misuse
 459     - Added "make coverage" and ENABLE_GCOV build option
 460
 461  * Changes in Yosys APIs
 462     - Added ConstEval defaultval feature
 463     - Added {get,set}_src_attribute() methods on RTLIL::AttrObject
 464     - Added SigSpec::is_fully_ones() and Const::is_fully_ones()
 465     - Added log_file_warning() and log_file_error() functions
 466
 467  * Formal Verification
 468     - Added "write_aiger"
 469     - Added "yosys-smtbmc --aig"
 470     - Added "always <positive_int>" to .smtc format
 471     - Added $cover cell type and support for cover properties
 472     - Added $fair/$live cell type and support for liveness properties
 473     - Added smtbmc support for memory vcd dumping
 474     - Added "chformal" command
 475     - Added "write_smt2 -stbv" and "write_smt2 -stdt"
 476     - Fix equiv_simple, old behavior now available with "equiv_simple -short"
 477     - Change to Yices2 as default SMT solver (it is GPL now)
 478     - Added "yosys-smtbmc --presat" (now default in SymbiYosys)
 479     - Added "yosys-smtbmc --smtc-init --smtc-top --noinit"
 480     - Added a brand new "write_btor" command for BTOR2
 481     - Added clk2fflogic memory support and other improvements
 482     - Added "async memory write" support to write_smt2
 483     - Simulate clock toggling in yosys-smtbmc VCD output
 484     - Added $allseq/$allconst cells for EA-solving
 485     - Make -nordff the default in "prep"
 486     - Added (* gclk *) attribute
 487     - Added "async2sync" pass for single-clock designs with async resets
 488
 489  * Verific support
 490     - Many improvements in Verific front-end
 491     - Added proper handling of concurent SVA properties
 492     - Map "const" and "rand const" to $anyseq/$anyconst
 493     - Added "verific -import -flatten" and "verific -import -extnets"
 494     - Added "verific -vlog-incdir -vlog-define -vlog-libdir"
 495     - Remove PSL support (because PSL has been removed in upstream Verific)
 496     - Improve integration with "hierarchy" command design elaboration
 497     - Added YOSYS_NOVERIFIC for running non-verific test cases with verific bin
 498     - Added simpilied "read" command that automatically uses verific if available
 499     - Added "verific -set-<severity> <msg_id>.."
 500     - Added "verific -work <libname>"
 501
 502  * New back-ends
 503     - Added initial Coolrunner-II support
 504     - Added initial eASIC support
 505     - Added initial ECP5 support
 506
 507  * GreenPAK Support
 508     - Added support for GP_DLATCH, GP_SPI, GP_DCMx, GP_COUNTx, etc.
 509
 510  * iCE40 Support
 511     - Add "synth_ice40 -vpr"
 512     - Add "synth_ice40 -nodffe"
 513     - Add "synth_ice40 -json"
 514     - Add Support for UltraPlus cells
 515
 516  * MAX10 and Cyclone IV Support
 517     - Added initial version of metacommand "synth_intel".
 518     - Improved write_verilog command to produce VQM netlist for Quartus Prime.
 519     - Added support for MAX10 FPGA family synthesis.
 520     - Added support for Cyclone IV family synthesis.
 521     - Added example of implementation for DE2i-150 board.
 522     - Added example of implementation for MAX10 development kit.
 523     - Added LFSR example from Asic World.
 524     - Added "dffinit -highlow" for mapping to Intel primitives
 525
 526
 527 Yosys 0.6 .. Yosys 0.7
 528 ----------------------
 529
 530  * Various
 531     - Added "yosys -D" feature
 532     - Added support for installed plugins in $(DATDIR)/plugins/
 533     - Renamed opt_const to opt_expr
 534     - Renamed opt_share to opt_merge
 535     - Added "prep -flatten" and "synth -flatten"
 536     - Added "prep -auto-top" and "synth -auto-top"
 537     - Using "mfs" and "lutpack" in ABC lut mapping
 538     - Support for abstract modules in chparam
 539     - Cleanup abstract modules at end of "hierarchy -top"
 540     - Added tristate buffer support to iopadmap
 541     - Added opt_expr support for div/mod by power-of-two
 542     - Added "select -assert-min <N> -assert-max <N>"
 543     - Added "attrmvcp" pass
 544     - Added "attrmap" command
 545     - Added "tee +INT -INT"
 546     - Added "zinit" pass
 547     - Added "setparam -type"
 548     - Added "shregmap" pass
 549     - Added "setundef -init"
 550     - Added "nlutmap -assert"
 551     - Added $sop cell type and "abc -sop -I <num> -P <num>"
 552     - Added "dc2" to default ABC scripts
 553     - Added "deminout"
 554     - Added "insbuf" command
 555     - Added "prep -nomem"
 556     - Added "opt_rmdff -keepdc"
 557     - Added "prep -nokeepdc"
 558     - Added initial version of "synth_gowin"
 559     - Added "fsm_expand -full"
 560     - Added support for fsm_encoding="user"
 561     - Many improvements in GreenPAK4 support
 562     - Added black box modules for all Xilinx 7-series lib cells
 563     - Added synth_ice40 support for latches via logic loops
 564     - Fixed ice40_opt lut unmapping, added "ice40_opt -unlut"
 565
 566  * Build System
 567     - Added ABCEXTERNAL and ABCURL make variables
 568     - Added BINDIR, LIBDIR, and DATDIR make variables
 569     - Added PKG_CONFIG make variable
 570     - Added SEED make variable (for "make test")
 571     - Added YOSYS_VER_STR make variable
 572     - Updated min GCC requirement to GCC 4.8
 573     - Updated required Bison version to Bison 3.x
 574
 575  * Internal APIs
 576     - Added ast.h to exported headers
 577     - Added ScriptPass helper class for script-like passes
 578     - Added CellEdgesDatabase API
 579
 580  * Front-ends and Back-ends
 581     - Added filename glob support to all front-ends
 582     - Added avail (black-box) module params to ilang format
 583     - Added $display %m support
 584     - Added support for $stop Verilog system task
 585     - Added support for SystemVerilog packages
 586     - Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b}
 587     - Added support for "active high" and "active low" latches in read_blif and write_blif
 588     - Use init value "2" for all uninitialized FFs in BLIF back-end
 589     - Added "read_blif -sop"
 590     - Added "write_blif -noalias"
 591     - Added various write_blif options for VTR support
 592     - write_json: also write module attributes.
 593     - Added "write_verilog -nodec -nostr -defparam"
 594     - Added "read_verilog -norestrict -assume-asserts"
 595     - Added support for bus interfaces to "read_liberty -lib"
 596     - Added liberty parser support for types within cell decls
 597     - Added "write_verilog -renameprefix -v"
 598     - Added "write_edif -nogndvcc"
 599
 600  * Formal Verification
 601     - Support for hierarchical designs in smt2 back-end
 602     - Yosys-smtbmc: Support for hierarchical VCD dumping
 603     - Added $initstate cell type and vlog function
 604     - Added $anyconst and $anyseq cell types and vlog functions
 605     - Added printing of code loc of failed asserts to yosys-smtbmc
 606     - Added memory_memx pass, "memory -memx", and "prep -memx"
 607     - Added "proc_mux -ifx"
 608     - Added "yosys-smtbmc -g"
 609     - Deprecated "write_smt2 -regs" (by default on now)
 610     - Made "write_smt2 -bv -mem" default, added "write_smt2 -nobv -nomem"
 611     - Added support for memories to smtio.py
 612     - Added "yosys-smtbmc --dump-vlogtb"
 613     - Added "yosys-smtbmc --smtc --dump-smtc"
 614     - Added "yosys-smtbmc --dump-all"
 615     - Added assertpmux command
 616     - Added "yosys-smtbmc --unroll"
 617     - Added $past, $stable, $rose, $fell SVA functions
 618     - Added "yosys-smtbmc --noinfo and --dummy"
 619     - Added "yosys-smtbmc --noincr"
 620     - Added "yosys-smtbmc --cex <filename>"
 621     - Added $ff and $_FF_ cell types
 622     - Added $global_clock verilog syntax support for creating $ff cells
 623     - Added clk2fflogic
 624
 625
 626 Yosys 0.5 .. Yosys 0.6
 627 ----------------------
 628
 629  * Various
 630      - Added Contributor Covenant Code of Conduct
 631      - Various improvements in dict<> and pool<>
 632      - Added hashlib::mfp and refactored SigMap
 633      - Improved support for reals as module parameters
 634      - Various improvements in SMT2 back-end
 635      - Added "keep_hierarchy" attribute
 636      - Verilog front-end: define `BLACKBOX in -lib mode
 637      - Added API for converting internal cells to AIGs
 638      - Added ENABLE_LIBYOSYS Makefile option
 639      - Removed "techmap -share_map" (use "-map +/filename" instead)
 640      - Switched all Python scripts to Python 3
 641      - Added support for $display()/$write() and $finish() to Verilog front-end
 642      - Added "yosys-smtbmc" formal verification flow
 643      - Added options for clang sanitizers to Makefile
 644
 645  * New commands and options
 646      - Added "scc -expect <N> -nofeedback"
 647      - Added "proc_dlatch"
 648      - Added "check"
 649      - Added "select %xe %cie %coe %M %C %R"
 650      - Added "sat -dump_json" (WaveJSON format)
 651      - Added "sat -tempinduct-baseonly -tempinduct-inductonly"
 652      - Added "sat -stepsize" and "sat -tempinduct-step"
 653      - Added "sat -show-regs -show-public -show-all"
 654      - Added "write_json" (Native Yosys JSON format)
 655      - Added "write_blif -attr"
 656      - Added "dffinit"
 657      - Added "chparam"
 658      - Added "muxcover"
 659      - Added "pmuxtree"
 660      - Added memory_bram "make_outreg" feature
 661      - Added "splice -wires"
 662      - Added "dff2dffe -direct-match"
 663      - Added simplemap $lut support
 664      - Added "read_blif"
 665      - Added "opt_share -share_all"
 666      - Added "aigmap"
 667      - Added "write_smt2 -mem -regs -wires"
 668      - Added "memory -nordff"
 669      - Added "write_smv"
 670      - Added "synth -nordff -noalumacc"
 671      - Added "rename -top new_name"
 672      - Added "opt_const -clkinv"
 673      - Added "synth -nofsm"
 674      - Added "miter -assert"
 675      - Added "read_verilog -noautowire"
 676      - Added "read_verilog -nodpi"
 677      - Added "tribuf"
 678      - Added "lut2mux"
 679      - Added "nlutmap"
 680      - Added "qwp"
 681      - Added "test_cell -noeval"
 682      - Added "edgetypes"
 683      - Added "equiv_struct"
 684      - Added "equiv_purge"
 685      - Added "equiv_mark"
 686      - Added "equiv_add -try -cell"
 687      - Added "singleton"
 688      - Added "abc -g -luts"
 689      - Added "torder"
 690      - Added "write_blif -cname"
 691      - Added "submod -copy"
 692      - Added "dffsr2dff"
 693      - Added "stat -liberty"
 694
 695  * Synthesis metacommands
 696      - Various improvements in synth_xilinx
 697      - Added synth_ice40 and synth_greenpak4
 698      - Added "prep" metacommand for "synthesis lite"
 699
 700  * Cell library changes
 701      - Added cell types to "help" system
 702      - Added $meminit cell type
 703      - Added $assume cell type
 704      - Added $_MUX4_, $_MUX8_, and $_MUX16_ cells
 705      - Added $tribuf and $_TBUF_ cell types
 706      - Added read-enable to memory model
 707
 708  * YosysJS
 709      - Various improvements in emscripten build
 710      - Added alternative webworker-based JS API
 711      - Added a few example applications
 712
 713
 714 Yosys 0.4 .. Yosys 0.5
 715 ----------------------
 716
 717  * API changes
 718      - Added log_warning()
 719      - Added eval_select_args() and eval_select_op()
 720      - Added cell->known(), cell->input(portname), cell->output(portname)
 721      - Skip blackbox modules in design->selected_modules()
 722      - Replaced std::map<> and std::set<> with dict<> and pool<>
 723      - New SigSpec::extend() is what used to be SigSpec::extend_u0()
 724      - Added YS_OVERRIDE, YS_FINAL, YS_ATTRIBUTE, YS_NORETURN
 725
 726  * Cell library changes
 727      - Added flip-flops with enable ($dffe etc.)
 728      - Added $equiv cells for equivalence checking framework
 729
 730  * Various
 731      - Updated ABC to hg rev 61ad5f908c03
 732      - Added clock domain partitioning to ABC pass
 733      - Improved plugin building (see "yosys-config --build")
 734      - Added ENABLE_NDEBUG Makefile flag for high-performance builds
 735      - Added "yosys -d", "yosys -L" and other driver improvements
 736      - Added support for multi-bit (array) cell ports to "write_edif"
 737      - Now printing most output to stdout, not stderr
 738      - Added "onehot" attribute (set by "fsm_map")
 739      - Various performance improvements
 740      - Vastly improved Xilinx flow
 741      - Added "make unsintall"
 742
 743  * Equivalence checking
 744      - Added equivalence checking commands:
 745          equiv_make equiv_simple equiv_status
 746          equiv_induct equiv_miter
 747          equiv_add equiv_remove
 748
 749  * Block RAM support:
 750      - Added "memory_bram" command
 751      - Added BRAM support to Xilinx flow
 752
 753  * Other New Commands and Options
 754      - Added "dff2dffe"
 755      - Added "fsm -encfile"
 756      - Added "dfflibmap -prepare"
 757      - Added "write_blid -unbuf -undef -blackbox"
 758      - Added "write_smt2" for writing SMT-LIBv2 files
 759      - Added "test_cell -w -muxdiv"
 760      - Added "select -read"
 761
 762
 763 Yosys 0.3.0 .. Yosys 0.4
 764 ------------------------
 765
 766  * Platform Support
 767      - Added support for mxe-based cross-builds for win32
 768      - Added sourcecode-export as VisualStudio project
 769      - Added experimental EMCC (JavaScript) support
 770
 771  * Verilog Frontend
 772      - Added -sv option for SystemVerilog (and automatic *.sv file support)
 773      - Added support for real-valued constants and constant expressions
 774      - Added support for non-standard "via_celltype" attribute on task/func
 775      - Added support for non-standard "module mod_name(...);" syntax
 776      - Added support for non-standard """ macro bodies
 777      - Added support for array with more than one dimension
 778      - Added support for $readmemh and $readmemb
 779      - Added support for DPI functions
 780
 781  * Changes in internal cell library
 782      - Added $shift and $shiftx cell types
 783      - Added $alu, $lcu, $fa and $macc cell types
 784      - Removed $bu0 and $safe_pmux cell types
 785      - $mem/$memwr WR_EN input is now a per-data-bit enable signal
 786      - Added $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
 787      - Renamed ports of $lut cells (from I->O to A->Y)
 788      - Renamed $_INV_ to $_NOT_
 789
 790  * Changes for simple synthesis flows
 791      - There is now a "synth" command with a recommended default script
 792      - Many improvements in synthesis of arithmetic functions to gates
 793          - Multipliers and adders with many operands are using carry-save adder trees
 794          - Remaining adders are now implemented using Brent-Kung carry look-ahead adders
 795      - Various new high-level optimizations on RTL netlist
 796      - Various improvements in FSM optimization
 797      - Updated ABC to hg 5b5af75f1dda (from 2014-11-07)
 798
 799  * Changes in internal APIs and RTLIL
 800      - Added log_id() and log_cell() helper functions
 801      - Added function-like cell creation helpers
 802      - Added GetSize() function (like .size() but with int)
 803      - Major refactoring of RTLIL::Module and related classes
 804      - Major refactoring of RTLIL::SigSpec and related classes
 805      - Now RTLIL::IdString is essentially an int
 806      - Added macros for code coverage counters
 807      - Added some Makefile magic for pretty make logs
 808      - Added "kernel/yosys.h" with all the core definitions
 809      - Changed a lot of code from FILE* to c++ streams
 810      - Added RTLIL::Monitor API and "trace" command
 811      - Added "Yosys" C++ namespace
 812
 813  * Changes relevant to SAT solving
 814      - Added ezSAT::keep_cnf() and ezSAT::non_incremental()
 815      - Added native ezSAT support for vector shift ops
 816      - Updated MiniSAT to git 37dc6c67e2 (from 2013-09-25)
 817
 818  * New commands (or large improvements to commands)
 819      - Added "synth" command with default script
 820      - Added "share" (finally some real resource sharing)
 821      - Added "memory_share" (reduce number of ports on memories)
 822      - Added "wreduce" and "alumacc" commands
 823      - Added "opt -keepdc -fine -full -fast"
 824      - Added some "test_*" commands
 825
 826  * Various other changes
 827      - Added %D and %c select operators
 828      - Added support for labels in yosys scripts
 829      - Added support for here-documents in yosys scripts
 830      - Support "+/" prefix for files from proc_share_dir
 831      - Added "autoidx" statement to ilang language
 832      - Switched from "yosys-svgviewer" to "xdot"
 833      - Renamed "stdcells.v" to "techmap.v"
 834      - Various bug fixes and small improvements
 835      - Improved welcome and bye messages
 836
 837
 838 Yosys 0.2.0 .. Yosys 0.3.0
 839 --------------------------
 840
 841  * Driver program and overall behavior:
 842      - Added "design -push" and "design -pop"
 843      - Added "tee" command for redirecting log output
 844
 845  * Changes in the internal cell library:
 846      - Added $dlatchsr and $_DLATCHSR_???_ cell types
 847
 848  * Improvements in Verilog frontend:
 849      - Improved support for const functions (case, always, repeat)
 850      - The generate..endgenerate keywords are now optional
 851      - Added support for arrays of module instances
 852      - Added support for "`default_nettype" directive
 853      - Added support for "`line" directive
 854
 855  * Other front- and back-ends:
 856      - Various changes to "write_blif" options
 857      - Various improvements in EDIF backend
 858      - Added "vhdl2verilog" pseudo-front-end
 859      - Added "verific" pseudo-front-end
 860
 861  * Improvements in technology mapping:
 862      - Added support for recursive techmap
 863      - Added CONSTMSK and CONSTVAL features to techmap
 864      - Added _TECHMAP_CONNMAP_*_ feature to techmap
 865      - Added _TECHMAP_REPLACE_ feature to techmap
 866      - Added "connwrappers" command for wrap-extract-unwrap method
 867      - Added "extract -map %<design_name>" feature
 868      - Added "extract -ignore_param ..." and "extract -ignore_parameters"
 869      - Added "techmap -max_iter" option
 870
 871  * Improvements to "eval" and "sat" framework:
 872      - Now include a copy of Minisat (with build fixes applied)
 873      - Switched to Minisat::SimpSolver as SAT back-end
 874      - Added "sat -dump_vcd" feature
 875      - Added "sat -dump_cnf" feature
 876      - Added "sat -initsteps <N>" feature
 877      - Added "freduce -stop <N>" feature
 878      - Added "freduce -dump <prefix>" feature
 879
 880  * Integration with ABC:
 881      - Updated ABC rev to 7600ffb9340c
 882
 883  * Improvements in the internal APIs:
 884      - Added RTLIL::Module::add... helper methods
 885      - Various build fixes for OSX (Darwin) and OpenBSD
 886
 887
 888 Yosys 0.1.0 .. Yosys 0.2.0
 889 --------------------------
 890
 891  * Changes to the driver program:
 892      - Added "yosys -h" and "yosys -H"
 893      - Added support for backslash line continuation in scripts
 894      - Added support for #-comments in same line as command
 895      - Added "echo" and "log" commands
 896
 897  * Improvements in Verilog frontend:
 898      - Added support for local registers in named blocks
 899      - Added support for "case" in "generate" blocks
 900      - Added support for $clog2 system function
 901      - Added support for basic SystemVerilog assert statements
 902      - Added preprocessor support for macro arguments
 903      - Added preprocessor support for `elsif statement
 904      - Added "verilog_defaults" command
 905      - Added read_verilog -icells option
 906      - Added support for constant sizes from parameters
 907      - Added "read_verilog -setattr"
 908      - Added support for function returning 'integer'
 909      - Added limited support for function calls in parameter values
 910      - Added "read_verilog -defer" to suppress evaluation of modules with default parameters
 911
 912  * Other front- and back-ends:
 913      - Added BTOR backend
 914      - Added Liberty frontend
 915
 916  * Improvements in technology mapping:
 917      - The "dfflibmap" command now strongly prefers solutions with
 918            no inverters in clock paths
 919      - The "dfflibmap" command now prefers cells with smaller area
 920      - Added support for multiple -map options to techmap
 921      - Added "dfflibmap" support for //-comments in liberty files
 922      - Added "memory_unpack" command to revert "memory_collect"
 923      - Added standard techmap rule "techmap -share_map pmux2mux.v"
 924      - Added "iopadmap -bits"
 925      - Added "setundef" command
 926      - Added "hilomap" command
 927
 928  * Changes in the internal cell library:
 929      - Major rewrite of simlib.v for better compatibility with other tools
 930      - Added PRIORITY parameter to $memwr cells
 931      - Added TRANSPARENT parameter to $memrd cells
 932      - Added RD_TRANSPARENT parameter to $mem cells
 933      - Added $bu0 cell (always 0-extend, even undef MSB)
 934      - Added $assert cell type
 935      - Added $slice and $concat cell types
 936
 937  * Integration with ABC:
 938      - Updated ABC to hg rev 2058c8ccea68
 939      - Tighter integration of ABC build with Yosys build. The make
 940            targets 'make abc' and 'make install-abc' are now obsolete.
 941      - Added support for passing FFs from one clock domain through ABC
 942      - Now always use BLIF as exchange format with ABC
 943      - Added support for "abc -script +<command_sequence>"
 944      - Improved standard ABC recipe
 945      - Added support for "keep" attribute to abc command
 946      - Added "abc -dff / -clk / -keepff" options
 947
 948  * Improvements to "eval" and "sat" framework:
 949      - Added support for "0" and "~0" in right-hand side -set expressions
 950      - Added "eval -set-undef" and "eval -table"
 951      - Added "sat -set-init" and "sat -set-init-*" for sequential problems
 952      - Added undef support to SAT solver, incl. various new "sat" options
 953      - Added correct support for === and !== for "eval" and "sat"
 954      - Added "sat -tempinduct" (default -seq is now non-induction sequential)
 955      - Added "sat -prove-asserts"
 956      - Complete rewrite of the 'freduce' command
 957      - Added "miter" command
 958      - Added "sat -show-inputs" and "sat -show-outputs"
 959      - Added "sat -ignore_unknown_cells" (now produce an error by default)
 960      - Added "sat -falsify"
 961      - Now "sat -verify" and "sat -falsify" can also be used without "-prove"
 962      - Added "expose" command
 963      - Added support for @<sel_name> to sat and eval signal expressions
 964
 965  * Changes in the 'make test' framework and auxiliary test tools:
 966      - Added autotest.sh -p and -f options
 967      - Replaced autotest.sh ISIM support with XSIM support
 968      - Added test cases for SAT framework
 969
 970  * Added "abbreviated IDs":
 971      - Now $<something>$foo can be abbreviated as $foo.
 972      - Usually this last part is a unique id (from RTLIL::autoidx)
 973      - This abbreviated IDs are now also used in "show" output
 974
 975  * Other changes to selection framework:
 976      - Now */ is optional in */<mode>:<arg> expressions
 977      - Added "select -assert-none" and "select -assert-any"
 978      - Added support for matching modules by attribute (A:<expr>)
 979      - Added "select -none"
 980      - Added support for r:<expr> pattern for matching cell parameters
 981      - Added support for !=, <, <=, >=, > for attribute and parameter matching
 982      - Added support for %s for selecting sub-modules
 983      - Added support for %m for expanding selections to whole modules
 984      - Added support for i:*, o:* and x:* pattern for selecting module ports
 985      - Added support for s:<expr> pattern for matching wire width
 986      - Added support for %a operation to select wire aliases
 987
 988  * Various other changes to commands and options:
 989      - The "ls" command now supports wildcards
 990      - Added "show -pause" and "show -format dot"
 991      - Added "show -color" support for cells
 992      - Added "show -label" and "show -notitle"
 993      - Added "dump -m" and "dump -n"
 994      - Added "history" command
 995      - Added "rename -hide"
 996      - Added "connect" command
 997      - Added "splitnets -driver"
 998      - Added "opt_const -mux_undef"
 999      - Added "opt_const -mux_bool"
1000      - Added "opt_const -undriven"
1001      - Added "opt -mux_undef -mux_bool -undriven -purge"
1002      - Added "hierarchy -libdir"
1003      - Added "hierarchy -purge_lib" (by default now do not remove lib cells)
1004      - Added "delete" command
1005      - Added "dump -append"
1006      - Added "setattr" and "setparam" commands
1007      - Added "design -stash/-copy-from/-copy-to"
1008      - Added "copy" command
1009      - Added "splice" command
1010