CHANGELOG

   1
   2 List of major changes and improvements between releases
   3 =======================================================
   4
   5 Yosys 0.10 .. Yosys 0.10-dev
   6 --------------------------
   7
   8  * Various
   9     - Added $aldff and $aldffe (flip-flops with async load) cells
  10
  11  * SystemVerilog
  12     - Fixed an issue which prevented writing directly to a memory word via a
  13       connection to an output port
  14     - Fixed an issue which prevented unbased unsized literals (e.g., `'1`) from
  15       filling the width of a cell input
  16     - Fixed an issue where connecting a slice covering the entirety of a signed
  17       signal to a cell input would cause a failed assertion
  18
  19  * Verific support
  20     - Importer support for {PRIM,WIDE_OPER}_DFF
  21     - Importer support for PRIM_BUFIF1
  22     - Option to use Verific without VHDL support
  23     - Importer support for {PRIM,WIDE_OPER}_DLATCH{,RS}
  24     - Added -cfg option for getting/setting Verific runtime flags
  25
  26 Yosys 0.9 .. Yosys 0.10
  27 --------------------------
  28
  29  * Various
  30     - Added automatic gzip decompression for frontends
  31     - Added $_NMUX_ cell type
  32     - Added automatic gzip compression (based on filename extension) for backends
  33     - Improve attribute and parameter encoding in JSON to avoid ambiguities between
  34       bit vectors and strings containing [01xz]*
  35     - Improvements in pmgen: subpattern and recursive matches
  36     - Support explicit FIRRTL properties
  37     - Improvements in pmgen: slices, choices, define, generate
  38     - Added "_TECHMAP_WIREINIT_*_" parameter and "_TECHMAP_REMOVEINIT_*_" wire for "techmap" pass
  39     - Added +/mul2dsp.v for decomposing wide multipliers to custom-sized ones
  40     - Added new frontend: rpc
  41     - Added --version and -version as aliases for -V
  42     - Improve yosys-smtbmc "solver not found" handling
  43     - Improved support of $readmem[hb] Memory Content File inclusion
  44     - Added CXXRTL backend
  45     - Use YosysHQ/abc instead of upstream berkeley-abc/abc
  46     - Added WASI platform support.
  47     - Added extmodule support to firrtl backend
  48     - Added $divfloor and $modfloor cells
  49     - Added $adffe, $dffsre, $sdff, $sdffe, $sdffce, $adlatch cells
  50     - Added "_TECHMAP_CELLNAME_" parameter for "techmap" pass
  51     - Added firrtl backend support for generic parameters in blackbox components
  52     - Added $meminit_v2 cells (with support for write mask)
  53     - Added $mem_v2, $memrd_v2, $memwr_v2, with the following features:
  54       - write priority masks, per write/write port pair
  55       - transparency and undefined collision behavior masks, per read/write port pair
  56       - read port reset and initialization
  57       - wide ports (accessing a naturally aligned power-of-two number of memory cells)
  58
  59  * New commands and options
  60     - Added "write_xaiger" backend
  61     - Added "read_xaiger"
  62     - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only)
  63     - Added "synth -abc9" (experimental)
  64     - Added "script -scriptwire"
  65     - Added "clkbufmap" pass
  66     - Added "extractinv" pass and "invertible_pin" attribute
  67     - Added "proc_clean -quiet"
  68     - Added "proc_prune" pass
  69     - Added "stat -tech cmos"
  70     - Added "opt_share" pass, run as part of "opt -full"
  71     - Added "-match-init" option to "dff2dffs" pass
  72     - Added "equiv_opt -multiclock"
  73     - Added "techmap_autopurge" support to techmap
  74     - Added "add -mod <modname[s]>"
  75     - Added "paramap" pass
  76     - Added "portlist" command
  77     - Added "check -mapped"
  78     - Added "check -allow-tbuf"
  79     - Added "autoname" pass
  80     - Added "write_verilog -extmem"
  81     - Added "opt_mem" pass
  82     - Added "scratchpad" pass
  83     - Added "fminit" pass
  84     - Added "opt_lut_ins" pass
  85     - Added "logger" pass
  86     - Added "show -nobg"
  87     - Added "exec" command
  88     - Added "design -delete"
  89     - Added "design -push-copy"
  90     - Added "qbfsat" command
  91     - Added "select -unset"
  92     - Added "dfflegalize" pass
  93     - Removed "opt_expr -clkinv" option, made it the default
  94     - Added "proc -nomux
  95     - Merged "dffsr2dff", "opt_rmdff", "dff2dffe", "dff2dffs", "peepopt.dffmux" passes into a new "opt_dff" pass
  96
  97  * SystemVerilog
  98     - Added checking of always block types (always_comb, always_latch and always_ff)
  99     - Added support for wildcard port connections (.*)
 100     - Added support for enum typedefs
 101     - Added support for structs and packed unions.
 102     - Allow constant function calls in for loops and generate if and case
 103     - Added support for static cast
 104     - Added support for logic typed parameters
 105     - Fixed generate scoping issues
 106     - Added support for real-valued parameters
 107     - Allow localparams in constant functions
 108     - Module name scope support
 109     - Support recursive functions using ternary expressions
 110     - Extended support for integer types
 111     - Support for parameters without default values
 112     - Allow globals in one file to depend on globals in another
 113     - Added support for: *=, /=, %=, <<=, >>=, <<<=, >>>=
 114     - Added support for parsing the 'bind' construct
 115     - support declaration in procedural for initialization
 116     - support declaration in generate for initialization
 117     - Support wand and wor of data types
 118
 119  * Verific support
 120     - Added "verific -L"
 121     - Add Verific SVA support for "always" properties
 122     - Add Verific support for SVA nexttime properties
 123     - Improve handling of verific primitives in "verific -import -V" mode
 124     - Import attributes for wires
 125     - Support VHDL enums
 126     - Added support for command files
 127
 128  * New back-ends
 129     - Added initial EFINIX support
 130     - Added Intel ALM: alternative synthesis for Intel FPGAs
 131     - Added initial Nexus support
 132     - Added initial MachXO2 support
 133     - Added initial QuickLogic PolarPro 3 support
 134
 135  * ECP5 support
 136     - Renamed labels/options in synth_ecp5 (e.g. dram -> map_lutram; -nodram -> -nolutram)
 137     - Added "synth_ecp5 -abc9" (experimental)
 138     - Added "synth_ecp5 -nowidelut"
 139     - "synth_ecp5" to now infer DSP blocks (-nodsp to disable, experimental)
 140
 141  * iCE40 support
 142     - Added "synth_ice40 -abc9" (experimental)
 143     - Added "synth_ice40 -device"
 144     - Renamed labels/options in synth_ice40 (e.g. dram -> map_lutram; -nodram -> -nolutram)
 145     - Added "ice40_wrapcarry" to encapsulate SB_LUT+SB_CARRY pairs for techmapping
 146     - Removed "ice40_unlut"
 147     - Added "ice40_dsp" for Lattice iCE40 DSP packing
 148     - "synth_ice40 -dsp" to infer DSP blocks
 149
 150  * Xilinx support
 151     - Added "synth_xilinx -abc9" (experimental)
 152     - Added "synth_xilinx -nocarry"
 153     - Added "synth_xilinx -nowidelut"
 154     - "synth_xilinx" to now infer wide multiplexers (-widemux <min> to enable)
 155     - Renamed labels/options in synth_xilinx (e.g. dram -> map_lutram; -nodram -> -nolutram)
 156     - Added "synth_xilinx -family xc6s" for Spartan 6 support (experimental)
 157     - Added "synth_xilinx -ise" (experimental)
 158     - Added "synth_xilinx -iopad"
 159     - "synth_xilinx" now automatically inserts clock buffers (add -noclkbuf to disable)
 160     - Added "xilinx_srl" for Xilinx shift register extraction
 161     - Removed "shregmap -tech xilinx" (superseded by "xilinx_srl")
 162     - Added "xilinx_dsp" for Xilinx DSP packing
 163     - "synth_xilinx" to now infer DSP blocks (-nodsp to disable)
 164     - Added latch support to synth_xilinx
 165     - Added support for flip-flops with synchronous reset to synth_xilinx
 166     - Added support for flip-flops with reset and enable to synth_xilinx
 167     - Added "xilinx_dffopt" pass
 168     - Added "synth_xilinx -dff"
 169
 170  * Intel support
 171     - Renamed labels in synth_intel (e.g. bram -> map_bram)
 172     - synth_intel: cyclone10 -> cyclone10lp, a10gx -> arria10gx
 173     - Added "intel_alm -abc9" (experimental)
 174
 175  * CoolRunner2 support
 176     - Separate and improve buffer cell insertion pass
 177     - Use extract_counter to optimize counters
 178
 179 Yosys 0.8 .. Yosys 0.9
 180 ----------------------
 181
 182  * Various
 183     - Many bugfixes and small improvements
 184     - Added support for SystemVerilog interfaces and modports
 185     - Added "write_edif -attrprop"
 186     - Added "opt_lut" pass
 187     - Added "gate2lut.v" techmap rule
 188     - Added "rename -src"
 189     - Added "equiv_opt" pass
 190     - Added "flowmap" LUT mapping pass
 191     - Added "rename -wire" to rename cells based on the wires they drive
 192     - Added "bugpoint" for creating minimised testcases
 193     - Added "write_edif -gndvccy"
 194     - "write_verilog" to escape Verilog keywords
 195     - Fixed sign handling of real constants
 196     - "write_verilog" to write initial statement for initial flop state
 197     - Added pmgen pattern matcher generator
 198     - Fixed opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_
 199     - Added "setundef -params" to replace undefined cell parameters
 200     - Renamed "yosys -D" to "yosys -U", added "yosys -D" to set Verilog defines
 201     - Fixed handling of defparam when default_nettype is none
 202     - Fixed "wreduce" flipflop handling
 203     - Fixed FIRRTL to Verilog process instance subfield assignment
 204     - Added "write_verilog -siminit"
 205     - Several fixes and improvements for mem2reg memories
 206     - Fixed handling of task output ports in clocked always blocks
 207     - Improved handling of and-with-1 and or-with-0 in "opt_expr"
 208     - Added "read_aiger" frontend
 209     - Added "mutate" pass
 210     - Added "hdlname" attribute
 211     - Added "rename -output"
 212     - Added "read_ilang -lib"
 213     - Improved "proc" full_case detection and handling
 214     - Added "whitebox" and "lib_whitebox" attributes
 215     - Added "read_verilog -nowb", "flatten -wb" and "wbflip"
 216     - Added Python bindings and support for Python plug-ins
 217     - Added "pmux2shiftx"
 218     - Added log_debug framework for reduced default verbosity
 219     - Improved "opt_expr" and "opt_clean" handling of (partially) undriven and/or unused wires
 220     - Added "peepopt" peephole optimisation pass using pmgen
 221     - Added approximate support for SystemVerilog "var" keyword
 222     - Added parsing of "specify" blocks into $specrule and $specify[23]
 223     - Added support for attributes on parameters and localparams
 224     - Added support for parsing attributes on port connections
 225     - Added "wreduce -keepdc"
 226     - Added support for optimising $dffe and $_DFFE_* cells in "opt_rmdff"
 227     - Added Verilog wand/wor wire type support
 228     - Added support for elaboration system tasks
 229     - Added "muxcover -mux{4,8,16}=<cost>"
 230     - Added "muxcover -dmux=<cost>"
 231     - Added "muxcover -nopartial"
 232     - Added "muxpack" pass
 233     - Added "pmux2shiftx -norange"
 234     - Added support for "~" in filename parsing
 235     - Added "read_verilog -pwires" feature to turn parameters into wires
 236     - Fixed sign extension of unsized constants with 'bx and 'bz MSB
 237     - Fixed genvar to be a signed type
 238     - Added support for attributes on case rules
 239     - Added "upto" and "offset" to JSON frontend and backend
 240     - Several liberty file parser improvements
 241     - Fixed handling of more complex BRAM patterns
 242     - Add "write_aiger -I -O -B"
 243
 244  * Formal Verification
 245     - Added $changed support to read_verilog
 246     - Added "read_verilog -noassert -noassume -assert-assumes"
 247     - Added btor ops for $mul, $div, $mod and $concat
 248     - Added yosys-smtbmc support for btor witnesses
 249     - Added "supercover" pass
 250     - Fixed $global_clock handling vs autowire
 251     - Added $dffsr support to "async2sync"
 252     - Added "fmcombine" pass
 253     - Added memory init support in "write_btor"
 254     - Added "cutpoint" pass
 255     - Changed "ne" to "neq" in btor2 output
 256     - Added support for SVA "final" keyword
 257     - Added "fmcombine -initeq -anyeq"
 258     - Added timescale and generated-by header to yosys-smtbmc vcd output
 259     - Improved BTOR2 handling of undriven wires
 260
 261  * Verific support
 262     - Enabled Verific flags vhdl_support_variable_slice and veri_elaborate_top_level_modules_having_interface_ports
 263     - Improved support for asymmetric memories
 264     - Added "verific -chparam"
 265     - Fixed "verific -extnets" for more complex situations
 266     - Added "read -verific" and "read -noverific"
 267     - Added "hierarchy -chparam"
 268
 269  * New back-ends
 270     - Added initial Anlogic support
 271     - Added initial SmartFusion2 and IGLOO2 support
 272
 273  * ECP5 support
 274     - Added "synth_ecp5 -nowidelut"
 275     - Added BRAM inference support to "synth_ecp5"
 276     - Added support for transforming Diamond IO and flipflop primitives
 277
 278  * iCE40 support
 279     - Added "ice40_unlut" pass
 280     - Added "synth_ice40 -relut"
 281     - Added "synth_ice40 -noabc"
 282     - Added "synth_ice40 -dffe_min_ce_use"
 283     - Added DSP inference support using pmgen
 284     - Added support for initialising BRAM primitives from a file
 285     - Added iCE40 Ultra RGB LED driver cells
 286
 287  * Xilinx support
 288     - Use "write_edif -pvector bra" for Xilinx EDIF files
 289     - Fixes for VPR place and route support with "synth_xilinx"
 290     - Added more cell simulation models
 291     - Added "synth_xilinx -family"
 292     - Added "stat -tech xilinx" to estimate logic cell usage
 293     - Added "synth_xilinx -nocarry"
 294     - Added "synth_xilinx -nowidelut"
 295     - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
 296     - Added support for mapping RAM32X1D
 297
 298 Yosys 0.7 .. Yosys 0.8
 299 ----------------------
 300
 301  * Various
 302     - Many bugfixes and small improvements
 303     - Strip debug symbols from installed binary
 304     - Replace -ignore_redef with -[no]overwrite in front-ends
 305     - Added write_verilog hex dump support, add -nohex option
 306     - Added "write_verilog -decimal"
 307     - Added "scc -set_attr"
 308     - Added "verilog_defines" command
 309     - Remember defines from one read_verilog to next
 310     - Added support for hierarchical defparam
 311     - Added FIRRTL back-end
 312     - Improved ABC default scripts
 313     - Added "design -reset-vlog"
 314     - Added "yosys -W regex", "yosys -w regex", and "yosys -e regex"
 315     - Added Verilog $rtoi and $itor support
 316     - Added "check -initdrv"
 317     - Added "read_blif -wideports"
 318     - Added support for SystemVerilog "++" and "--" operators
 319     - Added support for SystemVerilog unique, unique0, and priority case
 320     - Added "write_edif" options for edif "flavors"
 321     - Added support for resetall compiler directive
 322     - Added simple C beck-end (bitwise combinatorical only atm)
 323     - Added $_ANDNOT_ and $_ORNOT_ cell types
 324     - Added cell library aliases to "abc -g"
 325     - Added "setundef -anyseq"
 326     - Added "chtype" command
 327     - Added "design -import"
 328     - Added "write_table" command
 329     - Added "read_json" command
 330     - Added "sim" command
 331     - Added "extract_fa" and "extract_reduce" commands
 332     - Added "extract_counter" command
 333     - Added "opt_demorgan" command
 334     - Added support for $size and $bits SystemVerilog functions
 335     - Added "blackbox" command
 336     - Added "ltp" command
 337     - Added support for editline as replacement for readline
 338     - Added warnings for driver-driver conflicts between FFs (and other cells) and constants
 339     - Added "yosys -E" for creating Makefile dependencies files
 340     - Added "synth -noshare"
 341     - Added "memory_nordff"
 342     - Added "setundef -undef -expose -anyconst"
 343     - Added "expose -input"
 344     - Added specify/specparam parser support (simply ignore them)
 345     - Added "write_blif -inames -iattr"
 346     - Added "hierarchy -simcheck"
 347     - Added an option to statically link abc into yosys
 348     - Added protobuf back-end
 349     - Added BLIF parsing support for .conn and .cname
 350     - Added read_verilog error checking for reg/wire/logic misuse
 351     - Added "make coverage" and ENABLE_GCOV build option
 352
 353  * Changes in Yosys APIs
 354     - Added ConstEval defaultval feature
 355     - Added {get,set}_src_attribute() methods on RTLIL::AttrObject
 356     - Added SigSpec::is_fully_ones() and Const::is_fully_ones()
 357     - Added log_file_warning() and log_file_error() functions
 358
 359  * Formal Verification
 360     - Added "write_aiger"
 361     - Added "yosys-smtbmc --aig"
 362     - Added "always <positive_int>" to .smtc format
 363     - Added $cover cell type and support for cover properties
 364     - Added $fair/$live cell type and support for liveness properties
 365     - Added smtbmc support for memory vcd dumping
 366     - Added "chformal" command
 367     - Added "write_smt2 -stbv" and "write_smt2 -stdt"
 368     - Fix equiv_simple, old behavior now available with "equiv_simple -short"
 369     - Change to Yices2 as default SMT solver (it is GPL now)
 370     - Added "yosys-smtbmc --presat" (now default in SymbiYosys)
 371     - Added "yosys-smtbmc --smtc-init --smtc-top --noinit"
 372     - Added a brand new "write_btor" command for BTOR2
 373     - Added clk2fflogic memory support and other improvements
 374     - Added "async memory write" support to write_smt2
 375     - Simulate clock toggling in yosys-smtbmc VCD output
 376     - Added $allseq/$allconst cells for EA-solving
 377     - Make -nordff the default in "prep"
 378     - Added (* gclk *) attribute
 379     - Added "async2sync" pass for single-clock designs with async resets
 380
 381  * Verific support
 382     - Many improvements in Verific front-end
 383     - Added proper handling of concurent SVA properties
 384     - Map "const" and "rand const" to $anyseq/$anyconst
 385     - Added "verific -import -flatten" and "verific -import -extnets"
 386     - Added "verific -vlog-incdir -vlog-define -vlog-libdir"
 387     - Remove PSL support (because PSL has been removed in upstream Verific)
 388     - Improve integration with "hierarchy" command design elaboration
 389     - Added YOSYS_NOVERIFIC for running non-verific test cases with verific bin
 390     - Added simpilied "read" command that automatically uses verific if available
 391     - Added "verific -set-<severity> <msg_id>.."
 392     - Added "verific -work <libname>"
 393
 394  * New back-ends
 395     - Added initial Coolrunner-II support
 396     - Added initial eASIC support
 397     - Added initial ECP5 support
 398
 399  * GreenPAK Support
 400     - Added support for GP_DLATCH, GP_SPI, GP_DCMx, GP_COUNTx, etc.
 401
 402  * iCE40 Support
 403     - Add "synth_ice40 -vpr"
 404     - Add "synth_ice40 -nodffe"
 405     - Add "synth_ice40 -json"
 406     - Add Support for UltraPlus cells
 407
 408  * MAX10 and Cyclone IV Support
 409     - Added initial version of metacommand "synth_intel".
 410     - Improved write_verilog command to produce VQM netlist for Quartus Prime.
 411     - Added support for MAX10 FPGA family synthesis.
 412     - Added support for Cyclone IV family synthesis.
 413     - Added example of implementation for DE2i-150 board.
 414     - Added example of implementation for MAX10 development kit.
 415     - Added LFSR example from Asic World.
 416     - Added "dffinit -highlow" for mapping to Intel primitives
 417
 418
 419 Yosys 0.6 .. Yosys 0.7
 420 ----------------------
 421
 422  * Various
 423     - Added "yosys -D" feature
 424     - Added support for installed plugins in $(DATDIR)/plugins/
 425     - Renamed opt_const to opt_expr
 426     - Renamed opt_share to opt_merge
 427     - Added "prep -flatten" and "synth -flatten"
 428     - Added "prep -auto-top" and "synth -auto-top"
 429     - Using "mfs" and "lutpack" in ABC lut mapping
 430     - Support for abstract modules in chparam
 431     - Cleanup abstract modules at end of "hierarchy -top"
 432     - Added tristate buffer support to iopadmap
 433     - Added opt_expr support for div/mod by power-of-two
 434     - Added "select -assert-min <N> -assert-max <N>"
 435     - Added "attrmvcp" pass
 436     - Added "attrmap" command
 437     - Added "tee +INT -INT"
 438     - Added "zinit" pass
 439     - Added "setparam -type"
 440     - Added "shregmap" pass
 441     - Added "setundef -init"
 442     - Added "nlutmap -assert"
 443     - Added $sop cell type and "abc -sop -I <num> -P <num>"
 444     - Added "dc2" to default ABC scripts
 445     - Added "deminout"
 446     - Added "insbuf" command
 447     - Added "prep -nomem"
 448     - Added "opt_rmdff -keepdc"
 449     - Added "prep -nokeepdc"
 450     - Added initial version of "synth_gowin"
 451     - Added "fsm_expand -full"
 452     - Added support for fsm_encoding="user"
 453     - Many improvements in GreenPAK4 support
 454     - Added black box modules for all Xilinx 7-series lib cells
 455     - Added synth_ice40 support for latches via logic loops
 456     - Fixed ice40_opt lut unmapping, added "ice40_opt -unlut"
 457
 458  * Build System
 459     - Added ABCEXTERNAL and ABCURL make variables
 460     - Added BINDIR, LIBDIR, and DATDIR make variables
 461     - Added PKG_CONFIG make variable
 462     - Added SEED make variable (for "make test")
 463     - Added YOSYS_VER_STR make variable
 464     - Updated min GCC requirement to GCC 4.8
 465     - Updated required Bison version to Bison 3.x
 466
 467  * Internal APIs
 468     - Added ast.h to exported headers
 469     - Added ScriptPass helper class for script-like passes
 470     - Added CellEdgesDatabase API
 471
 472  * Front-ends and Back-ends
 473     - Added filename glob support to all front-ends
 474     - Added avail (black-box) module params to ilang format
 475     - Added $display %m support
 476     - Added support for $stop Verilog system task
 477     - Added support for SystemVerilog packages
 478     - Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b}
 479     - Added support for "active high" and "active low" latches in read_blif and write_blif
 480     - Use init value "2" for all uninitialized FFs in BLIF back-end
 481     - Added "read_blif -sop"
 482     - Added "write_blif -noalias"
 483     - Added various write_blif options for VTR support
 484     - write_json: also write module attributes.
 485     - Added "write_verilog -nodec -nostr -defparam"
 486     - Added "read_verilog -norestrict -assume-asserts"
 487     - Added support for bus interfaces to "read_liberty -lib"
 488     - Added liberty parser support for types within cell decls
 489     - Added "write_verilog -renameprefix -v"
 490     - Added "write_edif -nogndvcc"
 491
 492  * Formal Verification
 493     - Support for hierarchical designs in smt2 back-end
 494     - Yosys-smtbmc: Support for hierarchical VCD dumping
 495     - Added $initstate cell type and vlog function
 496     - Added $anyconst and $anyseq cell types and vlog functions
 497     - Added printing of code loc of failed asserts to yosys-smtbmc
 498     - Added memory_memx pass, "memory -memx", and "prep -memx"
 499     - Added "proc_mux -ifx"
 500     - Added "yosys-smtbmc -g"
 501     - Deprecated "write_smt2 -regs" (by default on now)
 502     - Made "write_smt2 -bv -mem" default, added "write_smt2 -nobv -nomem"
 503     - Added support for memories to smtio.py
 504     - Added "yosys-smtbmc --dump-vlogtb"
 505     - Added "yosys-smtbmc --smtc --dump-smtc"
 506     - Added "yosys-smtbmc --dump-all"
 507     - Added assertpmux command
 508     - Added "yosys-smtbmc --unroll"
 509     - Added $past, $stable, $rose, $fell SVA functions
 510     - Added "yosys-smtbmc --noinfo and --dummy"
 511     - Added "yosys-smtbmc --noincr"
 512     - Added "yosys-smtbmc --cex <filename>"
 513     - Added $ff and $_FF_ cell types
 514     - Added $global_clock verilog syntax support for creating $ff cells
 515     - Added clk2fflogic
 516
 517
 518 Yosys 0.5 .. Yosys 0.6
 519 ----------------------
 520
 521  * Various
 522      - Added Contributor Covenant Code of Conduct
 523      - Various improvements in dict<> and pool<>
 524      - Added hashlib::mfp and refactored SigMap
 525      - Improved support for reals as module parameters
 526      - Various improvements in SMT2 back-end
 527      - Added "keep_hierarchy" attribute
 528      - Verilog front-end: define `BLACKBOX in -lib mode
 529      - Added API for converting internal cells to AIGs
 530      - Added ENABLE_LIBYOSYS Makefile option
 531      - Removed "techmap -share_map" (use "-map +/filename" instead)
 532      - Switched all Python scripts to Python 3
 533      - Added support for $display()/$write() and $finish() to Verilog front-end
 534      - Added "yosys-smtbmc" formal verification flow
 535      - Added options for clang sanitizers to Makefile
 536
 537  * New commands and options
 538      - Added "scc -expect <N> -nofeedback"
 539      - Added "proc_dlatch"
 540      - Added "check"
 541      - Added "select %xe %cie %coe %M %C %R"
 542      - Added "sat -dump_json" (WaveJSON format)
 543      - Added "sat -tempinduct-baseonly -tempinduct-inductonly"
 544      - Added "sat -stepsize" and "sat -tempinduct-step"
 545      - Added "sat -show-regs -show-public -show-all"
 546      - Added "write_json" (Native Yosys JSON format)
 547      - Added "write_blif -attr"
 548      - Added "dffinit"
 549      - Added "chparam"
 550      - Added "muxcover"
 551      - Added "pmuxtree"
 552      - Added memory_bram "make_outreg" feature
 553      - Added "splice -wires"
 554      - Added "dff2dffe -direct-match"
 555      - Added simplemap $lut support
 556      - Added "read_blif"
 557      - Added "opt_share -share_all"
 558      - Added "aigmap"
 559      - Added "write_smt2 -mem -regs -wires"
 560      - Added "memory -nordff"
 561      - Added "write_smv"
 562      - Added "synth -nordff -noalumacc"
 563      - Added "rename -top new_name"
 564      - Added "opt_const -clkinv"
 565      - Added "synth -nofsm"
 566      - Added "miter -assert"
 567      - Added "read_verilog -noautowire"
 568      - Added "read_verilog -nodpi"
 569      - Added "tribuf"
 570      - Added "lut2mux"
 571      - Added "nlutmap"
 572      - Added "qwp"
 573      - Added "test_cell -noeval"
 574      - Added "edgetypes"
 575      - Added "equiv_struct"
 576      - Added "equiv_purge"
 577      - Added "equiv_mark"
 578      - Added "equiv_add -try -cell"
 579      - Added "singleton"
 580      - Added "abc -g -luts"
 581      - Added "torder"
 582      - Added "write_blif -cname"
 583      - Added "submod -copy"
 584      - Added "dffsr2dff"
 585      - Added "stat -liberty"
 586
 587  * Synthesis metacommands
 588      - Various improvements in synth_xilinx
 589      - Added synth_ice40 and synth_greenpak4
 590      - Added "prep" metacommand for "synthesis lite"
 591
 592  * Cell library changes
 593      - Added cell types to "help" system
 594      - Added $meminit cell type
 595      - Added $assume cell type
 596      - Added $_MUX4_, $_MUX8_, and $_MUX16_ cells
 597      - Added $tribuf and $_TBUF_ cell types
 598      - Added read-enable to memory model
 599
 600  * YosysJS
 601      - Various improvements in emscripten build
 602      - Added alternative webworker-based JS API
 603      - Added a few example applications
 604
 605
 606 Yosys 0.4 .. Yosys 0.5
 607 ----------------------
 608
 609  * API changes
 610      - Added log_warning()
 611      - Added eval_select_args() and eval_select_op()
 612      - Added cell->known(), cell->input(portname), cell->output(portname)
 613      - Skip blackbox modules in design->selected_modules()
 614      - Replaced std::map<> and std::set<> with dict<> and pool<>
 615      - New SigSpec::extend() is what used to be SigSpec::extend_u0()
 616      - Added YS_OVERRIDE, YS_FINAL, YS_ATTRIBUTE, YS_NORETURN
 617
 618  * Cell library changes
 619      - Added flip-flops with enable ($dffe etc.)
 620      - Added $equiv cells for equivalence checking framework
 621
 622  * Various
 623      - Updated ABC to hg rev 61ad5f908c03
 624      - Added clock domain partitioning to ABC pass
 625      - Improved plugin building (see "yosys-config --build")
 626      - Added ENABLE_NDEBUG Makefile flag for high-performance builds
 627      - Added "yosys -d", "yosys -L" and other driver improvements
 628      - Added support for multi-bit (array) cell ports to "write_edif"
 629      - Now printing most output to stdout, not stderr
 630      - Added "onehot" attribute (set by "fsm_map")
 631      - Various performance improvements
 632      - Vastly improved Xilinx flow
 633      - Added "make unsintall"
 634
 635  * Equivalence checking
 636      - Added equivalence checking commands:
 637          equiv_make equiv_simple equiv_status
 638          equiv_induct equiv_miter
 639          equiv_add equiv_remove
 640
 641  * Block RAM support:
 642      - Added "memory_bram" command
 643      - Added BRAM support to Xilinx flow
 644
 645  * Other New Commands and Options
 646      - Added "dff2dffe"
 647      - Added "fsm -encfile"
 648      - Added "dfflibmap -prepare"
 649      - Added "write_blid -unbuf -undef -blackbox"
 650      - Added "write_smt2" for writing SMT-LIBv2 files
 651      - Added "test_cell -w -muxdiv"
 652      - Added "select -read"
 653
 654
 655 Yosys 0.3.0 .. Yosys 0.4
 656 ------------------------
 657
 658  * Platform Support
 659      - Added support for mxe-based cross-builds for win32
 660      - Added sourcecode-export as VisualStudio project
 661      - Added experimental EMCC (JavaScript) support
 662
 663  * Verilog Frontend
 664      - Added -sv option for SystemVerilog (and automatic *.sv file support)
 665      - Added support for real-valued constants and constant expressions
 666      - Added support for non-standard "via_celltype" attribute on task/func
 667      - Added support for non-standard "module mod_name(...);" syntax
 668      - Added support for non-standard """ macro bodies
 669      - Added support for array with more than one dimension
 670      - Added support for $readmemh and $readmemb
 671      - Added support for DPI functions
 672
 673  * Changes in internal cell library
 674      - Added $shift and $shiftx cell types
 675      - Added $alu, $lcu, $fa and $macc cell types
 676      - Removed $bu0 and $safe_pmux cell types
 677      - $mem/$memwr WR_EN input is now a per-data-bit enable signal
 678      - Added $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
 679      - Renamed ports of $lut cells (from I->O to A->Y)
 680      - Renamed $_INV_ to $_NOT_
 681
 682  * Changes for simple synthesis flows
 683      - There is now a "synth" command with a recommended default script
 684      - Many improvements in synthesis of arithmetic functions to gates
 685          - Multipliers and adders with many operands are using carry-save adder trees
 686          - Remaining adders are now implemented using Brent-Kung carry look-ahead adders
 687      - Various new high-level optimizations on RTL netlist
 688      - Various improvements in FSM optimization
 689      - Updated ABC to hg 5b5af75f1dda (from 2014-11-07)
 690
 691  * Changes in internal APIs and RTLIL
 692      - Added log_id() and log_cell() helper functions
 693      - Added function-like cell creation helpers
 694      - Added GetSize() function (like .size() but with int)
 695      - Major refactoring of RTLIL::Module and related classes
 696      - Major refactoring of RTLIL::SigSpec and related classes
 697      - Now RTLIL::IdString is essentially an int
 698      - Added macros for code coverage counters
 699      - Added some Makefile magic for pretty make logs
 700      - Added "kernel/yosys.h" with all the core definitions
 701      - Changed a lot of code from FILE* to c++ streams
 702      - Added RTLIL::Monitor API and "trace" command
 703      - Added "Yosys" C++ namespace
 704
 705  * Changes relevant to SAT solving
 706      - Added ezSAT::keep_cnf() and ezSAT::non_incremental()
 707      - Added native ezSAT support for vector shift ops
 708      - Updated MiniSAT to git 37dc6c67e2 (from 2013-09-25)
 709
 710  * New commands (or large improvements to commands)
 711      - Added "synth" command with default script
 712      - Added "share" (finally some real resource sharing)
 713      - Added "memory_share" (reduce number of ports on memories)
 714      - Added "wreduce" and "alumacc" commands
 715      - Added "opt -keepdc -fine -full -fast"
 716      - Added some "test_*" commands
 717
 718  * Various other changes
 719      - Added %D and %c select operators
 720      - Added support for labels in yosys scripts
 721      - Added support for here-documents in yosys scripts
 722      - Support "+/" prefix for files from proc_share_dir
 723      - Added "autoidx" statement to ilang language
 724      - Switched from "yosys-svgviewer" to "xdot"
 725      - Renamed "stdcells.v" to "techmap.v"
 726      - Various bug fixes and small improvements
 727      - Improved welcome and bye messages
 728
 729
 730 Yosys 0.2.0 .. Yosys 0.3.0
 731 --------------------------
 732
 733  * Driver program and overall behavior:
 734      - Added "design -push" and "design -pop"
 735      - Added "tee" command for redirecting log output
 736
 737  * Changes in the internal cell library:
 738      - Added $dlatchsr and $_DLATCHSR_???_ cell types
 739
 740  * Improvements in Verilog frontend:
 741      - Improved support for const functions (case, always, repeat)
 742      - The generate..endgenerate keywords are now optional
 743      - Added support for arrays of module instances
 744      - Added support for "`default_nettype" directive
 745      - Added support for "`line" directive
 746
 747  * Other front- and back-ends:
 748      - Various changes to "write_blif" options
 749      - Various improvements in EDIF backend
 750      - Added "vhdl2verilog" pseudo-front-end
 751      - Added "verific" pseudo-front-end
 752
 753  * Improvements in technology mapping:
 754      - Added support for recursive techmap
 755      - Added CONSTMSK and CONSTVAL features to techmap
 756      - Added _TECHMAP_CONNMAP_*_ feature to techmap
 757      - Added _TECHMAP_REPLACE_ feature to techmap
 758      - Added "connwrappers" command for wrap-extract-unwrap method
 759      - Added "extract -map %<design_name>" feature
 760      - Added "extract -ignore_param ..." and "extract -ignore_parameters"
 761      - Added "techmap -max_iter" option
 762
 763  * Improvements to "eval" and "sat" framework:
 764      - Now include a copy of Minisat (with build fixes applied)
 765      - Switched to Minisat::SimpSolver as SAT back-end
 766      - Added "sat -dump_vcd" feature
 767      - Added "sat -dump_cnf" feature
 768      - Added "sat -initsteps <N>" feature
 769      - Added "freduce -stop <N>" feature
 770      - Added "freduce -dump <prefix>" feature
 771
 772  * Integration with ABC:
 773      - Updated ABC rev to 7600ffb9340c
 774
 775  * Improvements in the internal APIs:
 776      - Added RTLIL::Module::add... helper methods
 777      - Various build fixes for OSX (Darwin) and OpenBSD
 778
 779
 780 Yosys 0.1.0 .. Yosys 0.2.0
 781 --------------------------
 782
 783  * Changes to the driver program:
 784      - Added "yosys -h" and "yosys -H"
 785      - Added support for backslash line continuation in scripts
 786      - Added support for #-comments in same line as command
 787      - Added "echo" and "log" commands
 788
 789  * Improvements in Verilog frontend:
 790      - Added support for local registers in named blocks
 791      - Added support for "case" in "generate" blocks
 792      - Added support for $clog2 system function
 793      - Added support for basic SystemVerilog assert statements
 794      - Added preprocessor support for macro arguments
 795      - Added preprocessor support for `elsif statement
 796      - Added "verilog_defaults" command
 797      - Added read_verilog -icells option
 798      - Added support for constant sizes from parameters
 799      - Added "read_verilog -setattr"
 800      - Added support for function returning 'integer'
 801      - Added limited support for function calls in parameter values
 802      - Added "read_verilog -defer" to suppress evaluation of modules with default parameters
 803
 804  * Other front- and back-ends:
 805      - Added BTOR backend
 806      - Added Liberty frontend
 807
 808  * Improvements in technology mapping:
 809      - The "dfflibmap" command now strongly prefers solutions with
 810            no inverters in clock paths
 811      - The "dfflibmap" command now prefers cells with smaller area
 812      - Added support for multiple -map options to techmap
 813      - Added "dfflibmap" support for //-comments in liberty files
 814      - Added "memory_unpack" command to revert "memory_collect"
 815      - Added standard techmap rule "techmap -share_map pmux2mux.v"
 816      - Added "iopadmap -bits"
 817      - Added "setundef" command
 818      - Added "hilomap" command
 819
 820  * Changes in the internal cell library:
 821      - Major rewrite of simlib.v for better compatibility with other tools
 822      - Added PRIORITY parameter to $memwr cells
 823      - Added TRANSPARENT parameter to $memrd cells
 824      - Added RD_TRANSPARENT parameter to $mem cells
 825      - Added $bu0 cell (always 0-extend, even undef MSB)
 826      - Added $assert cell type
 827      - Added $slice and $concat cell types
 828
 829  * Integration with ABC:
 830      - Updated ABC to hg rev 2058c8ccea68
 831      - Tighter integration of ABC build with Yosys build. The make
 832            targets 'make abc' and 'make install-abc' are now obsolete.
 833      - Added support for passing FFs from one clock domain through ABC
 834      - Now always use BLIF as exchange format with ABC
 835      - Added support for "abc -script +<command_sequence>"
 836      - Improved standard ABC recipe
 837      - Added support for "keep" attribute to abc command
 838      - Added "abc -dff / -clk / -keepff" options
 839
 840  * Improvements to "eval" and "sat" framework:
 841      - Added support for "0" and "~0" in right-hand side -set expressions
 842      - Added "eval -set-undef" and "eval -table"
 843      - Added "sat -set-init" and "sat -set-init-*" for sequential problems
 844      - Added undef support to SAT solver, incl. various new "sat" options
 845      - Added correct support for === and !== for "eval" and "sat"
 846      - Added "sat -tempinduct" (default -seq is now non-induction sequential)
 847      - Added "sat -prove-asserts"
 848      - Complete rewrite of the 'freduce' command
 849      - Added "miter" command
 850      - Added "sat -show-inputs" and "sat -show-outputs"
 851      - Added "sat -ignore_unknown_cells" (now produce an error by default)
 852      - Added "sat -falsify"
 853      - Now "sat -verify" and "sat -falsify" can also be used without "-prove"
 854      - Added "expose" command
 855      - Added support for @<sel_name> to sat and eval signal expressions
 856
 857  * Changes in the 'make test' framework and auxiliary test tools:
 858      - Added autotest.sh -p and -f options
 859      - Replaced autotest.sh ISIM support with XSIM support
 860      - Added test cases for SAT framework
 861
 862  * Added "abbreviated IDs":
 863      - Now $<something>$foo can be abbreviated as $foo.
 864      - Usually this last part is a unique id (from RTLIL::autoidx)
 865      - This abbreviated IDs are now also used in "show" output
 866
 867  * Other changes to selection framework:
 868      - Now */ is optional in */<mode>:<arg> expressions
 869      - Added "select -assert-none" and "select -assert-any"
 870      - Added support for matching modules by attribute (A:<expr>)
 871      - Added "select -none"
 872      - Added support for r:<expr> pattern for matching cell parameters
 873      - Added support for !=, <, <=, >=, > for attribute and parameter matching
 874      - Added support for %s for selecting sub-modules
 875      - Added support for %m for expanding selections to whole modules
 876      - Added support for i:*, o:* and x:* pattern for selecting module ports
 877      - Added support for s:<expr> pattern for matching wire width
 878      - Added support for %a operation to select wire aliases
 879
 880  * Various other changes to commands and options:
 881      - The "ls" command now supports wildcards
 882      - Added "show -pause" and "show -format dot"
 883      - Added "show -color" support for cells
 884      - Added "show -label" and "show -notitle"
 885      - Added "dump -m" and "dump -n"
 886      - Added "history" command
 887      - Added "rename -hide"
 888      - Added "connect" command
 889      - Added "splitnets -driver"
 890      - Added "opt_const -mux_undef"
 891      - Added "opt_const -mux_bool"
 892      - Added "opt_const -undriven"
 893      - Added "opt -mux_undef -mux_bool -undriven -purge"
 894      - Added "hierarchy -libdir"
 895      - Added "hierarchy -purge_lib" (by default now do not remove lib cells)
 896      - Added "delete" command
 897      - Added "dump -append"
 898      - Added "setattr" and "setparam" commands
 899      - Added "design -stash/-copy-from/-copy-to"
 900      - Added "copy" command
 901      - Added "splice" command
 902