CHANGELOG

   1
   2 List of major changes and improvements between releases
   3 =======================================================
   4
   5
   6 Yosys 0.9 .. Yosys 0.9-dev
   7 --------------------------
   8
   9  * Various
  10     - Added "write_xaiger" backend
  11     - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only)
  12     - Added "synth_xilinx -abc9" (experimental)
  13     - Added "synth_ice40 -abc9" (experimental)
  14     - Added "synth -abc9" (experimental)
  15     - Added "script -scriptwire"
  16     - Added "synth_xilinx -nocarry"
  17     - Added "synth_xilinx -nowidelut"
  18     - Added "synth_ecp5 -nowidelut"
  19     - "synth_xilinx" to now infer wide multiplexers (-widemux <min> to enable)
  20     - Renamed labels/options in synth_ice40 (e.g. dram -> map_lutram; -nodram -> -nolutram)
  21     - Renamed labels/options in synth_ecp5 (e.g. dram -> map_lutram; -nodram -> -nolutram)
  22     - Renamed labels in synth_intel (e.g. bram -> map_bram)
  23     - Renamed labels/options in synth_xilinx (e.g. dram -> map_lutram; -nodram -> -nolutram)
  24     - Added automatic gzip decompression for frontends
  25     - Added $_NMUX_ cell type
  26     - Added automatic gzip compression (based on filename extension) for backends
  27     - Improve attribute and parameter encoding in JSON to avoid ambiguities between
  28       bit vectors and strings containing [01xz]*
  29     - Added "clkbufmap" pass
  30     - Added "extractinv" pass and "invertible_pin" attribute
  31     - Added "synth_xilinx -family xc6s" for Spartan 6 support (experimental)
  32     - Added "synth_xilinx -ise" (experimental)
  33     - Added "synth_xilinx -iopad"
  34     - "synth_xilinx" now automatically inserts clock buffers (add -noclkbuf to disable)
  35     - Improvements in pmgen: subpattern and recursive matches
  36     - Added "opt_share" pass, run as part of "opt -full"
  37     - Added "ice40_wrapcarry" to encapsulate SB_LUT+SB_CARRY pairs for techmapping
  38     - Removed "ice40_unlut"
  39     - Improvements in pmgen: slices, choices, define, generate
  40     - Added "xilinx_srl" for Xilinx shift register extraction
  41     - Removed "shregmap -tech xilinx" (superseded by "xilinx_srl")
  42     - Added "_TECHMAP_WIREINIT_*_" attribute and "_TECHMAP_REMOVEINIT_*_" wire for "techmap" pass
  43     - Added "-match-init" option to "dff2dffs" pass
  44     - Added "techmap_autopurge" support to techmap
  45     - Added "add -mod <modname[s]>"
  46     - Added +/mul2dsp.v for decomposing wide multipliers to custom-sized ones
  47     - Added "ice40_dsp" for Lattice iCE40 DSP packing
  48     - Added "xilinx_dsp" for Xilinx DSP packing
  49     - "synth_xilinx" to now infer DSP blocks (-nodsp to disable)
  50     - "synth_ecp5" to now infer DSP blocks (-nodsp to disable, experimental)
  51     - "synth_ice40 -dsp" to infer DSP blocks
  52     - Added latch support to synth_xilinx
  53     - Added support for flip-flops with synchronous reset to synth_xilinx
  54     - Added support for flip-flops with reset and enable to synth_xilinx
  55     - Added "check -mapped"
  56     - Added checking of SystemVerilog always block types (always_comb,
  57       always_latch and always_ff)
  58     - Added support for SystemVerilog wildcard port connections (.*)
  59     - Added "xilinx_dffopt" pass
  60     - Added "scratchpad" pass
  61     - Added "synth_xilinx -dff"
  62     - Improved support of $readmem[hb] Memory Content File inclusion
  63     - Added "opt_lut_ins" pass
  64     - Added "logger" pass
  65     - Removed "dffsr2dff" (use opt_rmdff instead)
  66     - Added "design -delete"
  67     - Added "select -unset"
  68     - Use YosysHQ/abc instead of upstream berkeley-abc/abc
  69     - Added $divfloor and $modfloor cells
  70
  71 Yosys 0.8 .. Yosys 0.9
  72 ----------------------
  73
  74  * Various
  75     - Many bugfixes and small improvements
  76     - Added support for SystemVerilog interfaces and modports
  77     - Added "write_edif -attrprop"
  78     - Added "opt_lut" pass
  79     - Added "gate2lut.v" techmap rule
  80     - Added "rename -src"
  81     - Added "equiv_opt" pass
  82     - Added "flowmap" LUT mapping pass
  83     - Added "rename -wire" to rename cells based on the wires they drive
  84     - Added "bugpoint" for creating minimised testcases
  85     - Added "write_edif -gndvccy"
  86     - "write_verilog" to escape Verilog keywords
  87     - Fixed sign handling of real constants
  88     - "write_verilog" to write initial statement for initial flop state
  89     - Added pmgen pattern matcher generator
  90     - Fixed opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_
  91     - Added "setundef -params" to replace undefined cell parameters
  92     - Renamed "yosys -D" to "yosys -U", added "yosys -D" to set Verilog defines
  93     - Fixed handling of defparam when default_nettype is none
  94     - Fixed "wreduce" flipflop handling
  95     - Fixed FIRRTL to Verilog process instance subfield assignment
  96     - Added "write_verilog -siminit"
  97     - Several fixes and improvements for mem2reg memories
  98     - Fixed handling of task output ports in clocked always blocks
  99     - Improved handling of and-with-1 and or-with-0 in "opt_expr"
 100     - Added "read_aiger" frontend
 101     - Added "mutate" pass
 102     - Added "hdlname" attribute
 103     - Added "rename -output"
 104     - Added "read_ilang -lib"
 105     - Improved "proc" full_case detection and handling
 106     - Added "whitebox" and "lib_whitebox" attributes
 107     - Added "read_verilog -nowb", "flatten -wb" and "wbflip"
 108     - Added Python bindings and support for Python plug-ins
 109     - Added "pmux2shiftx"
 110     - Added log_debug framework for reduced default verbosity
 111     - Improved "opt_expr" and "opt_clean" handling of (partially) undriven and/or unused wires
 112     - Added "peepopt" peephole optimisation pass using pmgen
 113     - Added approximate support for SystemVerilog "var" keyword
 114     - Added parsing of "specify" blocks into $specrule and $specify[23]
 115     - Added support for attributes on parameters and localparams
 116     - Added support for parsing attributes on port connections
 117     - Added "wreduce -keepdc"
 118     - Added support for optimising $dffe and $_DFFE_* cells in "opt_rmdff"
 119     - Added Verilog wand/wor wire type support
 120     - Added support for elaboration system tasks
 121     - Added "muxcover -mux{4,8,16}=<cost>"
 122     - Added "muxcover -dmux=<cost>"
 123     - Added "muxcover -nopartial"
 124     - Added "muxpack" pass
 125     - Added "pmux2shiftx -norange"
 126     - Added support for "~" in filename parsing
 127     - Added "read_verilog -pwires" feature to turn parameters into wires
 128     - Fixed sign extension of unsized constants with 'bx and 'bz MSB
 129     - Fixed genvar to be a signed type
 130     - Added support for attributes on case rules
 131     - Added "upto" and "offset" to JSON frontend and backend
 132     - Several liberty file parser improvements
 133     - Fixed handling of more complex BRAM patterns
 134     - Add "write_aiger -I -O -B"
 135
 136  * Formal Verification
 137     - Added $changed support to read_verilog
 138     - Added "read_verilog -noassert -noassume -assert-assumes"
 139     - Added btor ops for $mul, $div, $mod and $concat
 140     - Added yosys-smtbmc support for btor witnesses
 141     - Added "supercover" pass
 142     - Fixed $global_clock handling vs autowire
 143     - Added $dffsr support to "async2sync"
 144     - Added "fmcombine" pass
 145     - Added memory init support in "write_btor"
 146     - Added "cutpoint" pass
 147     - Changed "ne" to "neq" in btor2 output
 148     - Added support for SVA "final" keyword
 149     - Added "fmcombine -initeq -anyeq"
 150     - Added timescale and generated-by header to yosys-smtbmc vcd output
 151     - Improved BTOR2 handling of undriven wires
 152
 153  * Verific support
 154     - Enabled Verific flags vhdl_support_variable_slice and veri_elaborate_top_level_modules_having_interface_ports
 155     - Improved support for asymmetric memories
 156     - Added "verific -chparam"
 157     - Fixed "verific -extnets" for more complex situations
 158     - Added "read -verific" and "read -noverific"
 159     - Added "hierarchy -chparam"
 160
 161  * New back-ends
 162     - Added initial Anlogic support
 163     - Added initial SmartFusion2 and IGLOO2 support
 164
 165  * ECP5 support
 166     - Added "synth_ecp5 -nowidelut"
 167     - Added BRAM inference support to "synth_ecp5"
 168     - Added support for transforming Diamond IO and flipflop primitives
 169
 170  * iCE40 support
 171     - Added "ice40_unlut" pass
 172     - Added "synth_ice40 -relut"
 173     - Added "synth_ice40 -noabc"
 174     - Added "synth_ice40 -dffe_min_ce_use"
 175     - Added DSP inference support using pmgen
 176     - Added support for initialising BRAM primitives from a file
 177     - Added iCE40 Ultra RGB LED driver cells
 178
 179  * Xilinx support
 180     - Use "write_edif -pvector bra" for Xilinx EDIF files
 181     - Fixes for VPR place and route support with "synth_xilinx"
 182     - Added more cell simulation models
 183     - Added "synth_xilinx -family"
 184     - Added "stat -tech xilinx" to estimate logic cell usage
 185     - Added "synth_xilinx -nocarry"
 186     - Added "synth_xilinx -nowidelut"
 187     - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
 188     - Added support for mapping RAM32X1D
 189
 190 Yosys 0.7 .. Yosys 0.8
 191 ----------------------
 192
 193  * Various
 194     - Many bugfixes and small improvements
 195     - Strip debug symbols from installed binary
 196     - Replace -ignore_redef with -[no]overwrite in front-ends
 197     - Added write_verilog hex dump support, add -nohex option
 198     - Added "write_verilog -decimal"
 199     - Added "scc -set_attr"
 200     - Added "verilog_defines" command
 201     - Remember defines from one read_verilog to next
 202     - Added support for hierarchical defparam
 203     - Added FIRRTL back-end
 204     - Improved ABC default scripts
 205     - Added "design -reset-vlog"
 206     - Added "yosys -W regex", "yosys -w regex", and "yosys -e regex"
 207     - Added Verilog $rtoi and $itor support
 208     - Added "check -initdrv"
 209     - Added "read_blif -wideports"
 210     - Added support for SystemVerilog "++" and "--" operators
 211     - Added support for SystemVerilog unique, unique0, and priority case
 212     - Added "write_edif" options for edif "flavors"
 213     - Added support for resetall compiler directive
 214     - Added simple C beck-end (bitwise combinatorical only atm)
 215     - Added $_ANDNOT_ and $_ORNOT_ cell types
 216     - Added cell library aliases to "abc -g"
 217     - Added "setundef -anyseq"
 218     - Added "chtype" command
 219     - Added "design -import"
 220     - Added "write_table" command
 221     - Added "read_json" command
 222     - Added "sim" command
 223     - Added "extract_fa" and "extract_reduce" commands
 224     - Added "extract_counter" command
 225     - Added "opt_demorgan" command
 226     - Added support for $size and $bits SystemVerilog functions
 227     - Added "blackbox" command
 228     - Added "ltp" command
 229     - Added support for editline as replacement for readline
 230     - Added warnings for driver-driver conflicts between FFs (and other cells) and constants
 231     - Added "yosys -E" for creating Makefile dependencies files
 232     - Added "synth -noshare"
 233     - Added "memory_nordff"
 234     - Added "setundef -undef -expose -anyconst"
 235     - Added "expose -input"
 236     - Added specify/specparam parser support (simply ignore them)
 237     - Added "write_blif -inames -iattr"
 238     - Added "hierarchy -simcheck"
 239     - Added an option to statically link abc into yosys
 240     - Added protobuf back-end
 241     - Added BLIF parsing support for .conn and .cname
 242     - Added read_verilog error checking for reg/wire/logic misuse
 243     - Added "make coverage" and ENABLE_GCOV build option
 244
 245  * Changes in Yosys APIs
 246     - Added ConstEval defaultval feature
 247     - Added {get,set}_src_attribute() methods on RTLIL::AttrObject
 248     - Added SigSpec::is_fully_ones() and Const::is_fully_ones()
 249     - Added log_file_warning() and log_file_error() functions
 250
 251  * Formal Verification
 252     - Added "write_aiger"
 253     - Added "yosys-smtbmc --aig"
 254     - Added "always <positive_int>" to .smtc format
 255     - Added $cover cell type and support for cover properties
 256     - Added $fair/$live cell type and support for liveness properties
 257     - Added smtbmc support for memory vcd dumping
 258     - Added "chformal" command
 259     - Added "write_smt2 -stbv" and "write_smt2 -stdt"
 260     - Fix equiv_simple, old behavior now available with "equiv_simple -short"
 261     - Change to Yices2 as default SMT solver (it is GPL now)
 262     - Added "yosys-smtbmc --presat" (now default in SymbiYosys)
 263     - Added "yosys-smtbmc --smtc-init --smtc-top --noinit"
 264     - Added a brand new "write_btor" command for BTOR2
 265     - Added clk2fflogic memory support and other improvements
 266     - Added "async memory write" support to write_smt2
 267     - Simulate clock toggling in yosys-smtbmc VCD output
 268     - Added $allseq/$allconst cells for EA-solving
 269     - Make -nordff the default in "prep"
 270     - Added (* gclk *) attribute
 271     - Added "async2sync" pass for single-clock designs with async resets
 272
 273  * Verific support
 274     - Many improvements in Verific front-end
 275     - Added proper handling of concurent SVA properties
 276     - Map "const" and "rand const" to $anyseq/$anyconst
 277     - Added "verific -import -flatten" and "verific -import -extnets"
 278     - Added "verific -vlog-incdir -vlog-define -vlog-libdir"
 279     - Remove PSL support (because PSL has been removed in upstream Verific)
 280     - Improve integration with "hierarchy" command design elaboration
 281     - Added YOSYS_NOVERIFIC for running non-verific test cases with verific bin
 282     - Added simpilied "read" command that automatically uses verific if available
 283     - Added "verific -set-<severity> <msg_id>.."
 284     - Added "verific -work <libname>"
 285
 286  * New back-ends
 287     - Added initial Coolrunner-II support
 288     - Added initial eASIC support
 289     - Added initial ECP5 support
 290
 291  * GreenPAK Support
 292     - Added support for GP_DLATCH, GP_SPI, GP_DCMx, GP_COUNTx, etc.
 293
 294  * iCE40 Support
 295     - Add "synth_ice40 -vpr"
 296     - Add "synth_ice40 -nodffe"
 297     - Add "synth_ice40 -json"
 298     - Add Support for UltraPlus cells
 299
 300  * MAX10 and Cyclone IV Support
 301     - Added initial version of metacommand "synth_intel".
 302     - Improved write_verilog command to produce VQM netlist for Quartus Prime.
 303     - Added support for MAX10 FPGA family synthesis.
 304     - Added support for Cyclone IV family synthesis.
 305     - Added example of implementation for DE2i-150 board.
 306     - Added example of implementation for MAX10 development kit.
 307     - Added LFSR example from Asic World.
 308     - Added "dffinit -highlow" for mapping to Intel primitives
 309
 310
 311 Yosys 0.6 .. Yosys 0.7
 312 ----------------------
 313
 314  * Various
 315     - Added "yosys -D" feature
 316     - Added support for installed plugins in $(DATDIR)/plugins/
 317     - Renamed opt_const to opt_expr
 318     - Renamed opt_share to opt_merge
 319     - Added "prep -flatten" and "synth -flatten"
 320     - Added "prep -auto-top" and "synth -auto-top"
 321     - Using "mfs" and "lutpack" in ABC lut mapping
 322     - Support for abstract modules in chparam
 323     - Cleanup abstract modules at end of "hierarchy -top"
 324     - Added tristate buffer support to iopadmap
 325     - Added opt_expr support for div/mod by power-of-two
 326     - Added "select -assert-min <N> -assert-max <N>"
 327     - Added "attrmvcp" pass
 328     - Added "attrmap" command
 329     - Added "tee +INT -INT"
 330     - Added "zinit" pass
 331     - Added "setparam -type"
 332     - Added "shregmap" pass
 333     - Added "setundef -init"
 334     - Added "nlutmap -assert"
 335     - Added $sop cell type and "abc -sop -I <num> -P <num>"
 336     - Added "dc2" to default ABC scripts
 337     - Added "deminout"
 338     - Added "insbuf" command
 339     - Added "prep -nomem"
 340     - Added "opt_rmdff -keepdc"
 341     - Added "prep -nokeepdc"
 342     - Added initial version of "synth_gowin"
 343     - Added "fsm_expand -full"
 344     - Added support for fsm_encoding="user"
 345     - Many improvements in GreenPAK4 support
 346     - Added black box modules for all Xilinx 7-series lib cells
 347     - Added synth_ice40 support for latches via logic loops
 348     - Fixed ice40_opt lut unmapping, added "ice40_opt -unlut"
 349
 350  * Build System
 351     - Added ABCEXTERNAL and ABCURL make variables
 352     - Added BINDIR, LIBDIR, and DATDIR make variables
 353     - Added PKG_CONFIG make variable
 354     - Added SEED make variable (for "make test")
 355     - Added YOSYS_VER_STR make variable
 356     - Updated min GCC requirement to GCC 4.8
 357     - Updated required Bison version to Bison 3.x
 358
 359  * Internal APIs
 360     - Added ast.h to exported headers
 361     - Added ScriptPass helper class for script-like passes
 362     - Added CellEdgesDatabase API
 363
 364  * Front-ends and Back-ends
 365     - Added filename glob support to all front-ends
 366     - Added avail (black-box) module params to ilang format
 367     - Added $display %m support
 368     - Added support for $stop Verilog system task
 369     - Added support for SystemVerilog packages
 370     - Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b}
 371     - Added support for "active high" and "active low" latches in read_blif and write_blif
 372     - Use init value "2" for all uninitialized FFs in BLIF back-end
 373     - Added "read_blif -sop"
 374     - Added "write_blif -noalias"
 375     - Added various write_blif options for VTR support
 376     - write_json: also write module attributes.
 377     - Added "write_verilog -nodec -nostr -defparam"
 378     - Added "read_verilog -norestrict -assume-asserts"
 379     - Added support for bus interfaces to "read_liberty -lib"
 380     - Added liberty parser support for types within cell decls
 381     - Added "write_verilog -renameprefix -v"
 382     - Added "write_edif -nogndvcc"
 383
 384  * Formal Verification
 385     - Support for hierarchical designs in smt2 back-end
 386     - Yosys-smtbmc: Support for hierarchical VCD dumping
 387     - Added $initstate cell type and vlog function
 388     - Added $anyconst and $anyseq cell types and vlog functions
 389     - Added printing of code loc of failed asserts to yosys-smtbmc
 390     - Added memory_memx pass, "memory -memx", and "prep -memx"
 391     - Added "proc_mux -ifx"
 392     - Added "yosys-smtbmc -g"
 393     - Deprecated "write_smt2 -regs" (by default on now)
 394     - Made "write_smt2 -bv -mem" default, added "write_smt2 -nobv -nomem"
 395     - Added support for memories to smtio.py
 396     - Added "yosys-smtbmc --dump-vlogtb"
 397     - Added "yosys-smtbmc --smtc --dump-smtc"
 398     - Added "yosys-smtbmc --dump-all"
 399     - Added assertpmux command
 400     - Added "yosys-smtbmc --unroll"
 401     - Added $past, $stable, $rose, $fell SVA functions
 402     - Added "yosys-smtbmc --noinfo and --dummy"
 403     - Added "yosys-smtbmc --noincr"
 404     - Added "yosys-smtbmc --cex <filename>"
 405     - Added $ff and $_FF_ cell types
 406     - Added $global_clock verilog syntax support for creating $ff cells
 407     - Added clk2fflogic
 408
 409
 410 Yosys 0.5 .. Yosys 0.6
 411 ----------------------
 412
 413  * Various
 414      - Added Contributor Covenant Code of Conduct
 415      - Various improvements in dict<> and pool<>
 416      - Added hashlib::mfp and refactored SigMap
 417      - Improved support for reals as module parameters
 418      - Various improvements in SMT2 back-end
 419      - Added "keep_hierarchy" attribute
 420      - Verilog front-end: define `BLACKBOX in -lib mode
 421      - Added API for converting internal cells to AIGs
 422      - Added ENABLE_LIBYOSYS Makefile option
 423      - Removed "techmap -share_map" (use "-map +/filename" instead)
 424      - Switched all Python scripts to Python 3
 425      - Added support for $display()/$write() and $finish() to Verilog front-end
 426      - Added "yosys-smtbmc" formal verification flow
 427      - Added options for clang sanitizers to Makefile
 428
 429  * New commands and options
 430      - Added "scc -expect <N> -nofeedback"
 431      - Added "proc_dlatch"
 432      - Added "check"
 433      - Added "select %xe %cie %coe %M %C %R"
 434      - Added "sat -dump_json" (WaveJSON format)
 435      - Added "sat -tempinduct-baseonly -tempinduct-inductonly"
 436      - Added "sat -stepsize" and "sat -tempinduct-step"
 437      - Added "sat -show-regs -show-public -show-all"
 438      - Added "write_json" (Native Yosys JSON format)
 439      - Added "write_blif -attr"
 440      - Added "dffinit"
 441      - Added "chparam"
 442      - Added "muxcover"
 443      - Added "pmuxtree"
 444      - Added memory_bram "make_outreg" feature
 445      - Added "splice -wires"
 446      - Added "dff2dffe -direct-match"
 447      - Added simplemap $lut support
 448      - Added "read_blif"
 449      - Added "opt_share -share_all"
 450      - Added "aigmap"
 451      - Added "write_smt2 -mem -regs -wires"
 452      - Added "memory -nordff"
 453      - Added "write_smv"
 454      - Added "synth -nordff -noalumacc"
 455      - Added "rename -top new_name"
 456      - Added "opt_const -clkinv"
 457      - Added "synth -nofsm"
 458      - Added "miter -assert"
 459      - Added "read_verilog -noautowire"
 460      - Added "read_verilog -nodpi"
 461      - Added "tribuf"
 462      - Added "lut2mux"
 463      - Added "nlutmap"
 464      - Added "qwp"
 465      - Added "test_cell -noeval"
 466      - Added "edgetypes"
 467      - Added "equiv_struct"
 468      - Added "equiv_purge"
 469      - Added "equiv_mark"
 470      - Added "equiv_add -try -cell"
 471      - Added "singleton"
 472      - Added "abc -g -luts"
 473      - Added "torder"
 474      - Added "write_blif -cname"
 475      - Added "submod -copy"
 476      - Added "dffsr2dff"
 477      - Added "stat -liberty"
 478
 479  * Synthesis metacommands
 480      - Various improvements in synth_xilinx
 481      - Added synth_ice40 and synth_greenpak4
 482      - Added "prep" metacommand for "synthesis lite"
 483
 484  * Cell library changes
 485      - Added cell types to "help" system
 486      - Added $meminit cell type
 487      - Added $assume cell type
 488      - Added $_MUX4_, $_MUX8_, and $_MUX16_ cells
 489      - Added $tribuf and $_TBUF_ cell types
 490      - Added read-enable to memory model
 491
 492  * YosysJS
 493      - Various improvements in emscripten build
 494      - Added alternative webworker-based JS API
 495      - Added a few example applications
 496
 497
 498 Yosys 0.4 .. Yosys 0.5
 499 ----------------------
 500
 501  * API changes
 502      - Added log_warning()
 503      - Added eval_select_args() and eval_select_op()
 504      - Added cell->known(), cell->input(portname), cell->output(portname)
 505      - Skip blackbox modules in design->selected_modules()
 506      - Replaced std::map<> and std::set<> with dict<> and pool<>
 507      - New SigSpec::extend() is what used to be SigSpec::extend_u0()
 508      - Added YS_OVERRIDE, YS_FINAL, YS_ATTRIBUTE, YS_NORETURN
 509
 510  * Cell library changes
 511      - Added flip-flops with enable ($dffe etc.)
 512      - Added $equiv cells for equivalence checking framework
 513
 514  * Various
 515      - Updated ABC to hg rev 61ad5f908c03
 516      - Added clock domain partitioning to ABC pass
 517      - Improved plugin building (see "yosys-config --build")
 518      - Added ENABLE_NDEBUG Makefile flag for high-performance builds
 519      - Added "yosys -d", "yosys -L" and other driver improvements
 520      - Added support for multi-bit (array) cell ports to "write_edif"
 521      - Now printing most output to stdout, not stderr
 522      - Added "onehot" attribute (set by "fsm_map")
 523      - Various performance improvements
 524      - Vastly improved Xilinx flow
 525      - Added "make unsintall"
 526
 527  * Equivalence checking
 528      - Added equivalence checking commands:
 529          equiv_make equiv_simple equiv_status
 530          equiv_induct equiv_miter
 531          equiv_add equiv_remove
 532
 533  * Block RAM support:
 534      - Added "memory_bram" command
 535      - Added BRAM support to Xilinx flow
 536
 537  * Other New Commands and Options
 538      - Added "dff2dffe"
 539      - Added "fsm -encfile"
 540      - Added "dfflibmap -prepare"
 541      - Added "write_blid -unbuf -undef -blackbox"
 542      - Added "write_smt2" for writing SMT-LIBv2 files
 543      - Added "test_cell -w -muxdiv"
 544      - Added "select -read"
 545
 546
 547 Yosys 0.3.0 .. Yosys 0.4
 548 ------------------------
 549
 550  * Platform Support
 551      - Added support for mxe-based cross-builds for win32
 552      - Added sourcecode-export as VisualStudio project
 553      - Added experimental EMCC (JavaScript) support
 554
 555  * Verilog Frontend
 556      - Added -sv option for SystemVerilog (and automatic *.sv file support)
 557      - Added support for real-valued constants and constant expressions
 558      - Added support for non-standard "via_celltype" attribute on task/func
 559      - Added support for non-standard "module mod_name(...);" syntax
 560      - Added support for non-standard """ macro bodies
 561      - Added support for array with more than one dimension
 562      - Added support for $readmemh and $readmemb
 563      - Added support for DPI functions
 564
 565  * Changes in internal cell library
 566      - Added $shift and $shiftx cell types
 567      - Added $alu, $lcu, $fa and $macc cell types
 568      - Removed $bu0 and $safe_pmux cell types
 569      - $mem/$memwr WR_EN input is now a per-data-bit enable signal
 570      - Added $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
 571      - Renamed ports of $lut cells (from I->O to A->Y)
 572      - Renamed $_INV_ to $_NOT_
 573
 574  * Changes for simple synthesis flows
 575      - There is now a "synth" command with a recommended default script
 576      - Many improvements in synthesis of arithmetic functions to gates
 577          - Multipliers and adders with many operands are using carry-save adder trees
 578          - Remaining adders are now implemented using Brent-Kung carry look-ahead adders
 579      - Various new high-level optimizations on RTL netlist
 580      - Various improvements in FSM optimization
 581      - Updated ABC to hg 5b5af75f1dda (from 2014-11-07)
 582
 583  * Changes in internal APIs and RTLIL
 584      - Added log_id() and log_cell() helper functions
 585      - Added function-like cell creation helpers
 586      - Added GetSize() function (like .size() but with int)
 587      - Major refactoring of RTLIL::Module and related classes
 588      - Major refactoring of RTLIL::SigSpec and related classes
 589      - Now RTLIL::IdString is essentially an int
 590      - Added macros for code coverage counters
 591      - Added some Makefile magic for pretty make logs
 592      - Added "kernel/yosys.h" with all the core definitions
 593      - Changed a lot of code from FILE* to c++ streams
 594      - Added RTLIL::Monitor API and "trace" command
 595      - Added "Yosys" C++ namespace
 596
 597  * Changes relevant to SAT solving
 598      - Added ezSAT::keep_cnf() and ezSAT::non_incremental()
 599      - Added native ezSAT support for vector shift ops
 600      - Updated MiniSAT to git 37dc6c67e2 (from 2013-09-25)
 601
 602  * New commands (or large improvements to commands)
 603      - Added "synth" command with default script
 604      - Added "share" (finally some real resource sharing)
 605      - Added "memory_share" (reduce number of ports on memories)
 606      - Added "wreduce" and "alumacc" commands
 607      - Added "opt -keepdc -fine -full -fast"
 608      - Added some "test_*" commands
 609
 610  * Various other changes
 611      - Added %D and %c select operators
 612      - Added support for labels in yosys scripts
 613      - Added support for here-documents in yosys scripts
 614      - Support "+/" prefix for files from proc_share_dir
 615      - Added "autoidx" statement to ilang language
 616      - Switched from "yosys-svgviewer" to "xdot"
 617      - Renamed "stdcells.v" to "techmap.v"
 618      - Various bug fixes and small improvements
 619      - Improved welcome and bye messages
 620
 621
 622 Yosys 0.2.0 .. Yosys 0.3.0
 623 --------------------------
 624
 625  * Driver program and overall behavior:
 626      - Added "design -push" and "design -pop"
 627      - Added "tee" command for redirecting log output
 628
 629  * Changes in the internal cell library:
 630      - Added $dlatchsr and $_DLATCHSR_???_ cell types
 631
 632  * Improvements in Verilog frontend:
 633      - Improved support for const functions (case, always, repeat)
 634      - The generate..endgenerate keywords are now optional
 635      - Added support for arrays of module instances
 636      - Added support for "`default_nettype" directive
 637      - Added support for "`line" directive
 638
 639  * Other front- and back-ends:
 640      - Various changes to "write_blif" options
 641      - Various improvements in EDIF backend
 642      - Added "vhdl2verilog" pseudo-front-end
 643      - Added "verific" pseudo-front-end
 644
 645  * Improvements in technology mapping:
 646      - Added support for recursive techmap
 647      - Added CONSTMSK and CONSTVAL features to techmap
 648      - Added _TECHMAP_CONNMAP_*_ feature to techmap
 649      - Added _TECHMAP_REPLACE_ feature to techmap
 650      - Added "connwrappers" command for wrap-extract-unwrap method
 651      - Added "extract -map %<design_name>" feature
 652      - Added "extract -ignore_param ..." and "extract -ignore_parameters"
 653      - Added "techmap -max_iter" option
 654
 655  * Improvements to "eval" and "sat" framework:
 656      - Now include a copy of Minisat (with build fixes applied)
 657      - Switched to Minisat::SimpSolver as SAT back-end
 658      - Added "sat -dump_vcd" feature
 659      - Added "sat -dump_cnf" feature
 660      - Added "sat -initsteps <N>" feature
 661      - Added "freduce -stop <N>" feature
 662      - Added "freduce -dump <prefix>" feature
 663
 664  * Integration with ABC:
 665      - Updated ABC rev to 7600ffb9340c
 666
 667  * Improvements in the internal APIs:
 668      - Added RTLIL::Module::add... helper methods
 669      - Various build fixes for OSX (Darwin) and OpenBSD
 670
 671
 672 Yosys 0.1.0 .. Yosys 0.2.0
 673 --------------------------
 674
 675  * Changes to the driver program:
 676      - Added "yosys -h" and "yosys -H"
 677      - Added support for backslash line continuation in scripts
 678      - Added support for #-comments in same line as command
 679      - Added "echo" and "log" commands
 680
 681  * Improvements in Verilog frontend:
 682      - Added support for local registers in named blocks
 683      - Added support for "case" in "generate" blocks
 684      - Added support for $clog2 system function
 685      - Added support for basic SystemVerilog assert statements
 686      - Added preprocessor support for macro arguments
 687      - Added preprocessor support for `elsif statement
 688      - Added "verilog_defaults" command
 689      - Added read_verilog -icells option
 690      - Added support for constant sizes from parameters
 691      - Added "read_verilog -setattr"
 692      - Added support for function returning 'integer'
 693      - Added limited support for function calls in parameter values
 694      - Added "read_verilog -defer" to suppress evaluation of modules with default parameters
 695
 696  * Other front- and back-ends:
 697      - Added BTOR backend
 698      - Added Liberty frontend
 699
 700  * Improvements in technology mapping:
 701      - The "dfflibmap" command now strongly prefers solutions with
 702            no inverters in clock paths
 703      - The "dfflibmap" command now prefers cells with smaller area
 704      - Added support for multiple -map options to techmap
 705      - Added "dfflibmap" support for //-comments in liberty files
 706      - Added "memory_unpack" command to revert "memory_collect"
 707      - Added standard techmap rule "techmap -share_map pmux2mux.v"
 708      - Added "iopadmap -bits"
 709      - Added "setundef" command
 710      - Added "hilomap" command
 711
 712  * Changes in the internal cell library:
 713      - Major rewrite of simlib.v for better compatibility with other tools
 714      - Added PRIORITY parameter to $memwr cells
 715      - Added TRANSPARENT parameter to $memrd cells
 716      - Added RD_TRANSPARENT parameter to $mem cells
 717      - Added $bu0 cell (always 0-extend, even undef MSB)
 718      - Added $assert cell type
 719      - Added $slice and $concat cell types
 720
 721  * Integration with ABC:
 722      - Updated ABC to hg rev 2058c8ccea68
 723      - Tighter integration of ABC build with Yosys build. The make
 724            targets 'make abc' and 'make install-abc' are now obsolete.
 725      - Added support for passing FFs from one clock domain through ABC
 726      - Now always use BLIF as exchange format with ABC
 727      - Added support for "abc -script +<command_sequence>"
 728      - Improved standard ABC recipe
 729      - Added support for "keep" attribute to abc command
 730      - Added "abc -dff / -clk / -keepff" options
 731
 732  * Improvements to "eval" and "sat" framework:
 733      - Added support for "0" and "~0" in right-hand side -set expressions
 734      - Added "eval -set-undef" and "eval -table"
 735      - Added "sat -set-init" and "sat -set-init-*" for sequential problems
 736      - Added undef support to SAT solver, incl. various new "sat" options
 737      - Added correct support for === and !== for "eval" and "sat"
 738      - Added "sat -tempinduct" (default -seq is now non-induction sequential)
 739      - Added "sat -prove-asserts"
 740      - Complete rewrite of the 'freduce' command
 741      - Added "miter" command
 742      - Added "sat -show-inputs" and "sat -show-outputs"
 743      - Added "sat -ignore_unknown_cells" (now produce an error by default)
 744      - Added "sat -falsify"
 745      - Now "sat -verify" and "sat -falsify" can also be used without "-prove"
 746      - Added "expose" command
 747      - Added support for @<sel_name> to sat and eval signal expressions
 748
 749  * Changes in the 'make test' framework and auxiliary test tools:
 750      - Added autotest.sh -p and -f options
 751      - Replaced autotest.sh ISIM support with XSIM support
 752      - Added test cases for SAT framework
 753
 754  * Added "abbreviated IDs":
 755      - Now $<something>$foo can be abbreviated as $foo.
 756      - Usually this last part is a unique id (from RTLIL::autoidx)
 757      - This abbreviated IDs are now also used in "show" output
 758
 759  * Other changes to selection framework:
 760      - Now */ is optional in */<mode>:<arg> expressions
 761      - Added "select -assert-none" and "select -assert-any"
 762      - Added support for matching modules by attribute (A:<expr>)
 763      - Added "select -none"
 764      - Added support for r:<expr> pattern for matching cell parameters
 765      - Added support for !=, <, <=, >=, > for attribute and parameter matching
 766      - Added support for %s for selecting sub-modules
 767      - Added support for %m for expanding selections to whole modules
 768      - Added support for i:*, o:* and x:* pattern for selecting module ports
 769      - Added support for s:<expr> pattern for matching wire width
 770      - Added support for %a operation to select wire aliases
 771
 772  * Various other changes to commands and options:
 773      - The "ls" command now supports wildcards
 774      - Added "show -pause" and "show -format dot"
 775      - Added "show -color" support for cells
 776      - Added "show -label" and "show -notitle"
 777      - Added "dump -m" and "dump -n"
 778      - Added "history" command
 779      - Added "rename -hide"
 780      - Added "connect" command
 781      - Added "splitnets -driver"
 782      - Added "opt_const -mux_undef"
 783      - Added "opt_const -mux_bool"
 784      - Added "opt_const -undriven"
 785      - Added "opt -mux_undef -mux_bool -undriven -purge"
 786      - Added "hierarchy -libdir"
 787      - Added "hierarchy -purge_lib" (by default now do not remove lib cells)
 788      - Added "delete" command
 789      - Added "dump -append"
 790      - Added "setattr" and "setparam" commands
 791      - Added "design -stash/-copy-from/-copy-to"
 792      - Added "copy" command
 793      - Added "splice" command
 794