CHANGELOG

   1
   2 List of major changes and improvements between releases
   3 =======================================================
   4
   5 Yosys 0.14 .. Yosys 0.14-dev
   6 --------------------------
   7
   8  * Verilog
   9     - Fixed evaluation of constant functions with variables or arguments with
  10       reversed dimensions
  11     - Fixed elaboration of dynamic range assignments where the vector is
  12       reversed or is not zero-indexed
  13     - Added frontend support for time scale delay values (e.g., `#1ns`)
  14
  15  * SystemVerilog
  16     - Added support for accessing whole sub-structures in expressions
  17
  18 Yosys 0.13 .. Yosys 0.14
  19 --------------------------
  20
  21  * Various
  22     - Added $bmux and $demux cells and related optimization patterns.
  23
  24  * New commands and options
  25     - Added "bmuxmap" and "dmuxmap" passes
  26     - Added "-fst" option to "sim" pass for writing FST files
  27     - Added "-r", "-scope", "-start", "-stop", "-at", "-sim", "-sim-gate",
  28       "-sim-gold" options to "sim" pass for co-simulation
  29
  30  * Anlogic support
  31     - Added support for BRAMs
  32
  33 Yosys 0.12 .. Yosys 0.13
  34 --------------------------
  35
  36  * Various
  37     - Use "read" command to parse HDL files from Yosys command-line
  38     - Added "yosys -r <topmodule>" command line option
  39     - write_verilog: dump zero width sigspecs correctly
  40
  41  * SystemVerilog
  42     - Fixed regression preventing the use array querying functions in case
  43       expressions and case item expressions
  44     - Fixed static size casts inadvertently limiting the result width of binary
  45       operations
  46     - Fixed static size casts ignoring expression signedness
  47     - Fixed static size casts not extending unbased unsized literals
  48     - Added automatic `nosync` inference for local variables in `always_comb`
  49       procedures which are always assigned before they are used to avoid errant
  50       latch inference
  51
  52  * New commands and options
  53     - Added "clean_zerowidth" pass
  54
  55  * Verific support
  56     - Add YOSYS to the implicitly defined verilog macros in verific
  57
  58 Yosys 0.11 .. Yosys 0.12
  59 --------------------------
  60
  61  * Various
  62     - Added iopadmap native support for negative-polarity output enable
  63     - ABC update
  64
  65  * SystemVerilog
  66     - Support parameters using struct as a wiretype
  67
  68  * New commands and options
  69     - Added "-genlib" option to "abc" pass
  70     - Added "sta" very crude static timing analysis pass
  71
  72  * Verific support
  73     - Fixed memory block size in import
  74
  75  * New back-ends
  76     - Added support for GateMate FPGA from Cologne Chip AG
  77
  78  * Intel ALM support
  79     - Added preliminary Arria V support
  80
  81
  82 Yosys 0.10 .. Yosys 0.11
  83 --------------------------
  84
  85  * Various
  86     - Added $aldff and $aldffe (flip-flops with async load) cells
  87
  88  * SystemVerilog
  89     - Fixed an issue which prevented writing directly to a memory word via a
  90       connection to an output port
  91     - Fixed an issue which prevented unbased unsized literals (e.g., `'1`) from
  92       filling the width of a cell input
  93     - Fixed an issue where connecting a slice covering the entirety of a signed
  94       signal to a cell input would cause a failed assertion
  95
  96  * Verific support
  97     - Importer support for {PRIM,WIDE_OPER}_DFF
  98     - Importer support for PRIM_BUFIF1
  99     - Option to use Verific without VHDL support
 100     - Importer support for {PRIM,WIDE_OPER}_DLATCH{,RS}
 101     - Added -cfg option for getting/setting Verific runtime flags
 102
 103 Yosys 0.9 .. Yosys 0.10
 104 --------------------------
 105
 106  * Various
 107     - Added automatic gzip decompression for frontends
 108     - Added $_NMUX_ cell type
 109     - Added automatic gzip compression (based on filename extension) for backends
 110     - Improve attribute and parameter encoding in JSON to avoid ambiguities between
 111       bit vectors and strings containing [01xz]*
 112     - Improvements in pmgen: subpattern and recursive matches
 113     - Support explicit FIRRTL properties
 114     - Improvements in pmgen: slices, choices, define, generate
 115     - Added "_TECHMAP_WIREINIT_*_" parameter and "_TECHMAP_REMOVEINIT_*_" wire for "techmap" pass
 116     - Added +/mul2dsp.v for decomposing wide multipliers to custom-sized ones
 117     - Added new frontend: rpc
 118     - Added --version and -version as aliases for -V
 119     - Improve yosys-smtbmc "solver not found" handling
 120     - Improved support of $readmem[hb] Memory Content File inclusion
 121     - Added CXXRTL backend
 122     - Use YosysHQ/abc instead of upstream berkeley-abc/abc
 123     - Added WASI platform support.
 124     - Added extmodule support to firrtl backend
 125     - Added $divfloor and $modfloor cells
 126     - Added $adffe, $dffsre, $sdff, $sdffe, $sdffce, $adlatch cells
 127     - Added "_TECHMAP_CELLNAME_" parameter for "techmap" pass
 128     - Added firrtl backend support for generic parameters in blackbox components
 129     - Added $meminit_v2 cells (with support for write mask)
 130     - Added $mem_v2, $memrd_v2, $memwr_v2, with the following features:
 131       - write priority masks, per write/write port pair
 132       - transparency and undefined collision behavior masks, per read/write port pair
 133       - read port reset and initialization
 134       - wide ports (accessing a naturally aligned power-of-two number of memory cells)
 135
 136  * New commands and options
 137     - Added "write_xaiger" backend
 138     - Added "read_xaiger"
 139     - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only)
 140     - Added "synth -abc9" (experimental)
 141     - Added "script -scriptwire"
 142     - Added "clkbufmap" pass
 143     - Added "extractinv" pass and "invertible_pin" attribute
 144     - Added "proc_clean -quiet"
 145     - Added "proc_prune" pass
 146     - Added "stat -tech cmos"
 147     - Added "opt_share" pass, run as part of "opt -full"
 148     - Added "-match-init" option to "dff2dffs" pass
 149     - Added "equiv_opt -multiclock"
 150     - Added "techmap_autopurge" support to techmap
 151     - Added "add -mod <modname[s]>"
 152     - Added "paramap" pass
 153     - Added "portlist" command
 154     - Added "check -mapped"
 155     - Added "check -allow-tbuf"
 156     - Added "autoname" pass
 157     - Added "write_verilog -extmem"
 158     - Added "opt_mem" pass
 159     - Added "scratchpad" pass
 160     - Added "fminit" pass
 161     - Added "opt_lut_ins" pass
 162     - Added "logger" pass
 163     - Added "show -nobg"
 164     - Added "exec" command
 165     - Added "design -delete"
 166     - Added "design -push-copy"
 167     - Added "qbfsat" command
 168     - Added "select -unset"
 169     - Added "dfflegalize" pass
 170     - Removed "opt_expr -clkinv" option, made it the default
 171     - Added "proc -nomux
 172     - Merged "dffsr2dff", "opt_rmdff", "dff2dffe", "dff2dffs", "peepopt.dffmux" passes into a new "opt_dff" pass
 173
 174  * SystemVerilog
 175     - Added checking of always block types (always_comb, always_latch and always_ff)
 176     - Added support for wildcard port connections (.*)
 177     - Added support for enum typedefs
 178     - Added support for structs and packed unions.
 179     - Allow constant function calls in for loops and generate if and case
 180     - Added support for static cast
 181     - Added support for logic typed parameters
 182     - Fixed generate scoping issues
 183     - Added support for real-valued parameters
 184     - Allow localparams in constant functions
 185     - Module name scope support
 186     - Support recursive functions using ternary expressions
 187     - Extended support for integer types
 188     - Support for parameters without default values
 189     - Allow globals in one file to depend on globals in another
 190     - Added support for: *=, /=, %=, <<=, >>=, <<<=, >>>=
 191     - Added support for parsing the 'bind' construct
 192     - support declaration in procedural for initialization
 193     - support declaration in generate for initialization
 194     - Support wand and wor of data types
 195
 196  * Verific support
 197     - Added "verific -L"
 198     - Add Verific SVA support for "always" properties
 199     - Add Verific support for SVA nexttime properties
 200     - Improve handling of verific primitives in "verific -import -V" mode
 201     - Import attributes for wires
 202     - Support VHDL enums
 203     - Added support for command files
 204
 205  * New back-ends
 206     - Added initial EFINIX support
 207     - Added Intel ALM: alternative synthesis for Intel FPGAs
 208     - Added initial Nexus support
 209     - Added initial MachXO2 support
 210     - Added initial QuickLogic PolarPro 3 support
 211
 212  * ECP5 support
 213     - Renamed labels/options in synth_ecp5 (e.g. dram -> map_lutram; -nodram -> -nolutram)
 214     - Added "synth_ecp5 -abc9" (experimental)
 215     - Added "synth_ecp5 -nowidelut"
 216     - "synth_ecp5" to now infer DSP blocks (-nodsp to disable, experimental)
 217
 218  * iCE40 support
 219     - Added "synth_ice40 -abc9" (experimental)
 220     - Added "synth_ice40 -device"
 221     - Renamed labels/options in synth_ice40 (e.g. dram -> map_lutram; -nodram -> -nolutram)
 222     - Added "ice40_wrapcarry" to encapsulate SB_LUT+SB_CARRY pairs for techmapping
 223     - Removed "ice40_unlut"
 224     - Added "ice40_dsp" for Lattice iCE40 DSP packing
 225     - "synth_ice40 -dsp" to infer DSP blocks
 226
 227  * Xilinx support
 228     - Added "synth_xilinx -abc9" (experimental)
 229     - Added "synth_xilinx -nocarry"
 230     - Added "synth_xilinx -nowidelut"
 231     - "synth_xilinx" to now infer wide multiplexers (-widemux <min> to enable)
 232     - Renamed labels/options in synth_xilinx (e.g. dram -> map_lutram; -nodram -> -nolutram)
 233     - Added "synth_xilinx -family xc6s" for Spartan 6 support (experimental)
 234     - Added "synth_xilinx -ise" (experimental)
 235     - Added "synth_xilinx -iopad"
 236     - "synth_xilinx" now automatically inserts clock buffers (add -noclkbuf to disable)
 237     - Added "xilinx_srl" for Xilinx shift register extraction
 238     - Removed "shregmap -tech xilinx" (superseded by "xilinx_srl")
 239     - Added "xilinx_dsp" for Xilinx DSP packing
 240     - "synth_xilinx" to now infer DSP blocks (-nodsp to disable)
 241     - Added latch support to synth_xilinx
 242     - Added support for flip-flops with synchronous reset to synth_xilinx
 243     - Added support for flip-flops with reset and enable to synth_xilinx
 244     - Added "xilinx_dffopt" pass
 245     - Added "synth_xilinx -dff"
 246
 247  * Intel support
 248     - Renamed labels in synth_intel (e.g. bram -> map_bram)
 249     - synth_intel: cyclone10 -> cyclone10lp, a10gx -> arria10gx
 250     - Added "intel_alm -abc9" (experimental)
 251
 252  * CoolRunner2 support
 253     - Separate and improve buffer cell insertion pass
 254     - Use extract_counter to optimize counters
 255
 256 Yosys 0.8 .. Yosys 0.9
 257 ----------------------
 258
 259  * Various
 260     - Many bugfixes and small improvements
 261     - Added support for SystemVerilog interfaces and modports
 262     - Added "write_edif -attrprop"
 263     - Added "opt_lut" pass
 264     - Added "gate2lut.v" techmap rule
 265     - Added "rename -src"
 266     - Added "equiv_opt" pass
 267     - Added "flowmap" LUT mapping pass
 268     - Added "rename -wire" to rename cells based on the wires they drive
 269     - Added "bugpoint" for creating minimised testcases
 270     - Added "write_edif -gndvccy"
 271     - "write_verilog" to escape Verilog keywords
 272     - Fixed sign handling of real constants
 273     - "write_verilog" to write initial statement for initial flop state
 274     - Added pmgen pattern matcher generator
 275     - Fixed opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_
 276     - Added "setundef -params" to replace undefined cell parameters
 277     - Renamed "yosys -D" to "yosys -U", added "yosys -D" to set Verilog defines
 278     - Fixed handling of defparam when default_nettype is none
 279     - Fixed "wreduce" flipflop handling
 280     - Fixed FIRRTL to Verilog process instance subfield assignment
 281     - Added "write_verilog -siminit"
 282     - Several fixes and improvements for mem2reg memories
 283     - Fixed handling of task output ports in clocked always blocks
 284     - Improved handling of and-with-1 and or-with-0 in "opt_expr"
 285     - Added "read_aiger" frontend
 286     - Added "mutate" pass
 287     - Added "hdlname" attribute
 288     - Added "rename -output"
 289     - Added "read_ilang -lib"
 290     - Improved "proc" full_case detection and handling
 291     - Added "whitebox" and "lib_whitebox" attributes
 292     - Added "read_verilog -nowb", "flatten -wb" and "wbflip"
 293     - Added Python bindings and support for Python plug-ins
 294     - Added "pmux2shiftx"
 295     - Added log_debug framework for reduced default verbosity
 296     - Improved "opt_expr" and "opt_clean" handling of (partially) undriven and/or unused wires
 297     - Added "peepopt" peephole optimisation pass using pmgen
 298     - Added approximate support for SystemVerilog "var" keyword
 299     - Added parsing of "specify" blocks into $specrule and $specify[23]
 300     - Added support for attributes on parameters and localparams
 301     - Added support for parsing attributes on port connections
 302     - Added "wreduce -keepdc"
 303     - Added support for optimising $dffe and $_DFFE_* cells in "opt_rmdff"
 304     - Added Verilog wand/wor wire type support
 305     - Added support for elaboration system tasks
 306     - Added "muxcover -mux{4,8,16}=<cost>"
 307     - Added "muxcover -dmux=<cost>"
 308     - Added "muxcover -nopartial"
 309     - Added "muxpack" pass
 310     - Added "pmux2shiftx -norange"
 311     - Added support for "~" in filename parsing
 312     - Added "read_verilog -pwires" feature to turn parameters into wires
 313     - Fixed sign extension of unsized constants with 'bx and 'bz MSB
 314     - Fixed genvar to be a signed type
 315     - Added support for attributes on case rules
 316     - Added "upto" and "offset" to JSON frontend and backend
 317     - Several liberty file parser improvements
 318     - Fixed handling of more complex BRAM patterns
 319     - Add "write_aiger -I -O -B"
 320
 321  * Formal Verification
 322     - Added $changed support to read_verilog
 323     - Added "read_verilog -noassert -noassume -assert-assumes"
 324     - Added btor ops for $mul, $div, $mod and $concat
 325     - Added yosys-smtbmc support for btor witnesses
 326     - Added "supercover" pass
 327     - Fixed $global_clock handling vs autowire
 328     - Added $dffsr support to "async2sync"
 329     - Added "fmcombine" pass
 330     - Added memory init support in "write_btor"
 331     - Added "cutpoint" pass
 332     - Changed "ne" to "neq" in btor2 output
 333     - Added support for SVA "final" keyword
 334     - Added "fmcombine -initeq -anyeq"
 335     - Added timescale and generated-by header to yosys-smtbmc vcd output
 336     - Improved BTOR2 handling of undriven wires
 337
 338  * Verific support
 339     - Enabled Verific flags vhdl_support_variable_slice and veri_elaborate_top_level_modules_having_interface_ports
 340     - Improved support for asymmetric memories
 341     - Added "verific -chparam"
 342     - Fixed "verific -extnets" for more complex situations
 343     - Added "read -verific" and "read -noverific"
 344     - Added "hierarchy -chparam"
 345
 346  * New back-ends
 347     - Added initial Anlogic support
 348     - Added initial SmartFusion2 and IGLOO2 support
 349
 350  * ECP5 support
 351     - Added "synth_ecp5 -nowidelut"
 352     - Added BRAM inference support to "synth_ecp5"
 353     - Added support for transforming Diamond IO and flipflop primitives
 354
 355  * iCE40 support
 356     - Added "ice40_unlut" pass
 357     - Added "synth_ice40 -relut"
 358     - Added "synth_ice40 -noabc"
 359     - Added "synth_ice40 -dffe_min_ce_use"
 360     - Added DSP inference support using pmgen
 361     - Added support for initialising BRAM primitives from a file
 362     - Added iCE40 Ultra RGB LED driver cells
 363
 364  * Xilinx support
 365     - Use "write_edif -pvector bra" for Xilinx EDIF files
 366     - Fixes for VPR place and route support with "synth_xilinx"
 367     - Added more cell simulation models
 368     - Added "synth_xilinx -family"
 369     - Added "stat -tech xilinx" to estimate logic cell usage
 370     - Added "synth_xilinx -nocarry"
 371     - Added "synth_xilinx -nowidelut"
 372     - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
 373     - Added support for mapping RAM32X1D
 374
 375 Yosys 0.7 .. Yosys 0.8
 376 ----------------------
 377
 378  * Various
 379     - Many bugfixes and small improvements
 380     - Strip debug symbols from installed binary
 381     - Replace -ignore_redef with -[no]overwrite in front-ends
 382     - Added write_verilog hex dump support, add -nohex option
 383     - Added "write_verilog -decimal"
 384     - Added "scc -set_attr"
 385     - Added "verilog_defines" command
 386     - Remember defines from one read_verilog to next
 387     - Added support for hierarchical defparam
 388     - Added FIRRTL back-end
 389     - Improved ABC default scripts
 390     - Added "design -reset-vlog"
 391     - Added "yosys -W regex", "yosys -w regex", and "yosys -e regex"
 392     - Added Verilog $rtoi and $itor support
 393     - Added "check -initdrv"
 394     - Added "read_blif -wideports"
 395     - Added support for SystemVerilog "++" and "--" operators
 396     - Added support for SystemVerilog unique, unique0, and priority case
 397     - Added "write_edif" options for edif "flavors"
 398     - Added support for resetall compiler directive
 399     - Added simple C beck-end (bitwise combinatorical only atm)
 400     - Added $_ANDNOT_ and $_ORNOT_ cell types
 401     - Added cell library aliases to "abc -g"
 402     - Added "setundef -anyseq"
 403     - Added "chtype" command
 404     - Added "design -import"
 405     - Added "write_table" command
 406     - Added "read_json" command
 407     - Added "sim" command
 408     - Added "extract_fa" and "extract_reduce" commands
 409     - Added "extract_counter" command
 410     - Added "opt_demorgan" command
 411     - Added support for $size and $bits SystemVerilog functions
 412     - Added "blackbox" command
 413     - Added "ltp" command
 414     - Added support for editline as replacement for readline
 415     - Added warnings for driver-driver conflicts between FFs (and other cells) and constants
 416     - Added "yosys -E" for creating Makefile dependencies files
 417     - Added "synth -noshare"
 418     - Added "memory_nordff"
 419     - Added "setundef -undef -expose -anyconst"
 420     - Added "expose -input"
 421     - Added specify/specparam parser support (simply ignore them)
 422     - Added "write_blif -inames -iattr"
 423     - Added "hierarchy -simcheck"
 424     - Added an option to statically link abc into yosys
 425     - Added protobuf back-end
 426     - Added BLIF parsing support for .conn and .cname
 427     - Added read_verilog error checking for reg/wire/logic misuse
 428     - Added "make coverage" and ENABLE_GCOV build option
 429
 430  * Changes in Yosys APIs
 431     - Added ConstEval defaultval feature
 432     - Added {get,set}_src_attribute() methods on RTLIL::AttrObject
 433     - Added SigSpec::is_fully_ones() and Const::is_fully_ones()
 434     - Added log_file_warning() and log_file_error() functions
 435
 436  * Formal Verification
 437     - Added "write_aiger"
 438     - Added "yosys-smtbmc --aig"
 439     - Added "always <positive_int>" to .smtc format
 440     - Added $cover cell type and support for cover properties
 441     - Added $fair/$live cell type and support for liveness properties
 442     - Added smtbmc support for memory vcd dumping
 443     - Added "chformal" command
 444     - Added "write_smt2 -stbv" and "write_smt2 -stdt"
 445     - Fix equiv_simple, old behavior now available with "equiv_simple -short"
 446     - Change to Yices2 as default SMT solver (it is GPL now)
 447     - Added "yosys-smtbmc --presat" (now default in SymbiYosys)
 448     - Added "yosys-smtbmc --smtc-init --smtc-top --noinit"
 449     - Added a brand new "write_btor" command for BTOR2
 450     - Added clk2fflogic memory support and other improvements
 451     - Added "async memory write" support to write_smt2
 452     - Simulate clock toggling in yosys-smtbmc VCD output
 453     - Added $allseq/$allconst cells for EA-solving
 454     - Make -nordff the default in "prep"
 455     - Added (* gclk *) attribute
 456     - Added "async2sync" pass for single-clock designs with async resets
 457
 458  * Verific support
 459     - Many improvements in Verific front-end
 460     - Added proper handling of concurent SVA properties
 461     - Map "const" and "rand const" to $anyseq/$anyconst
 462     - Added "verific -import -flatten" and "verific -import -extnets"
 463     - Added "verific -vlog-incdir -vlog-define -vlog-libdir"
 464     - Remove PSL support (because PSL has been removed in upstream Verific)
 465     - Improve integration with "hierarchy" command design elaboration
 466     - Added YOSYS_NOVERIFIC for running non-verific test cases with verific bin
 467     - Added simpilied "read" command that automatically uses verific if available
 468     - Added "verific -set-<severity> <msg_id>.."
 469     - Added "verific -work <libname>"
 470
 471  * New back-ends
 472     - Added initial Coolrunner-II support
 473     - Added initial eASIC support
 474     - Added initial ECP5 support
 475
 476  * GreenPAK Support
 477     - Added support for GP_DLATCH, GP_SPI, GP_DCMx, GP_COUNTx, etc.
 478
 479  * iCE40 Support
 480     - Add "synth_ice40 -vpr"
 481     - Add "synth_ice40 -nodffe"
 482     - Add "synth_ice40 -json"
 483     - Add Support for UltraPlus cells
 484
 485  * MAX10 and Cyclone IV Support
 486     - Added initial version of metacommand "synth_intel".
 487     - Improved write_verilog command to produce VQM netlist for Quartus Prime.
 488     - Added support for MAX10 FPGA family synthesis.
 489     - Added support for Cyclone IV family synthesis.
 490     - Added example of implementation for DE2i-150 board.
 491     - Added example of implementation for MAX10 development kit.
 492     - Added LFSR example from Asic World.
 493     - Added "dffinit -highlow" for mapping to Intel primitives
 494
 495
 496 Yosys 0.6 .. Yosys 0.7
 497 ----------------------
 498
 499  * Various
 500     - Added "yosys -D" feature
 501     - Added support for installed plugins in $(DATDIR)/plugins/
 502     - Renamed opt_const to opt_expr
 503     - Renamed opt_share to opt_merge
 504     - Added "prep -flatten" and "synth -flatten"
 505     - Added "prep -auto-top" and "synth -auto-top"
 506     - Using "mfs" and "lutpack" in ABC lut mapping
 507     - Support for abstract modules in chparam
 508     - Cleanup abstract modules at end of "hierarchy -top"
 509     - Added tristate buffer support to iopadmap
 510     - Added opt_expr support for div/mod by power-of-two
 511     - Added "select -assert-min <N> -assert-max <N>"
 512     - Added "attrmvcp" pass
 513     - Added "attrmap" command
 514     - Added "tee +INT -INT"
 515     - Added "zinit" pass
 516     - Added "setparam -type"
 517     - Added "shregmap" pass
 518     - Added "setundef -init"
 519     - Added "nlutmap -assert"
 520     - Added $sop cell type and "abc -sop -I <num> -P <num>"
 521     - Added "dc2" to default ABC scripts
 522     - Added "deminout"
 523     - Added "insbuf" command
 524     - Added "prep -nomem"
 525     - Added "opt_rmdff -keepdc"
 526     - Added "prep -nokeepdc"
 527     - Added initial version of "synth_gowin"
 528     - Added "fsm_expand -full"
 529     - Added support for fsm_encoding="user"
 530     - Many improvements in GreenPAK4 support
 531     - Added black box modules for all Xilinx 7-series lib cells
 532     - Added synth_ice40 support for latches via logic loops
 533     - Fixed ice40_opt lut unmapping, added "ice40_opt -unlut"
 534
 535  * Build System
 536     - Added ABCEXTERNAL and ABCURL make variables
 537     - Added BINDIR, LIBDIR, and DATDIR make variables
 538     - Added PKG_CONFIG make variable
 539     - Added SEED make variable (for "make test")
 540     - Added YOSYS_VER_STR make variable
 541     - Updated min GCC requirement to GCC 4.8
 542     - Updated required Bison version to Bison 3.x
 543
 544  * Internal APIs
 545     - Added ast.h to exported headers
 546     - Added ScriptPass helper class for script-like passes
 547     - Added CellEdgesDatabase API
 548
 549  * Front-ends and Back-ends
 550     - Added filename glob support to all front-ends
 551     - Added avail (black-box) module params to ilang format
 552     - Added $display %m support
 553     - Added support for $stop Verilog system task
 554     - Added support for SystemVerilog packages
 555     - Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b}
 556     - Added support for "active high" and "active low" latches in read_blif and write_blif
 557     - Use init value "2" for all uninitialized FFs in BLIF back-end
 558     - Added "read_blif -sop"
 559     - Added "write_blif -noalias"
 560     - Added various write_blif options for VTR support
 561     - write_json: also write module attributes.
 562     - Added "write_verilog -nodec -nostr -defparam"
 563     - Added "read_verilog -norestrict -assume-asserts"
 564     - Added support for bus interfaces to "read_liberty -lib"
 565     - Added liberty parser support for types within cell decls
 566     - Added "write_verilog -renameprefix -v"
 567     - Added "write_edif -nogndvcc"
 568
 569  * Formal Verification
 570     - Support for hierarchical designs in smt2 back-end
 571     - Yosys-smtbmc: Support for hierarchical VCD dumping
 572     - Added $initstate cell type and vlog function
 573     - Added $anyconst and $anyseq cell types and vlog functions
 574     - Added printing of code loc of failed asserts to yosys-smtbmc
 575     - Added memory_memx pass, "memory -memx", and "prep -memx"
 576     - Added "proc_mux -ifx"
 577     - Added "yosys-smtbmc -g"
 578     - Deprecated "write_smt2 -regs" (by default on now)
 579     - Made "write_smt2 -bv -mem" default, added "write_smt2 -nobv -nomem"
 580     - Added support for memories to smtio.py
 581     - Added "yosys-smtbmc --dump-vlogtb"
 582     - Added "yosys-smtbmc --smtc --dump-smtc"
 583     - Added "yosys-smtbmc --dump-all"
 584     - Added assertpmux command
 585     - Added "yosys-smtbmc --unroll"
 586     - Added $past, $stable, $rose, $fell SVA functions
 587     - Added "yosys-smtbmc --noinfo and --dummy"
 588     - Added "yosys-smtbmc --noincr"
 589     - Added "yosys-smtbmc --cex <filename>"
 590     - Added $ff and $_FF_ cell types
 591     - Added $global_clock verilog syntax support for creating $ff cells
 592     - Added clk2fflogic
 593
 594
 595 Yosys 0.5 .. Yosys 0.6
 596 ----------------------
 597
 598  * Various
 599      - Added Contributor Covenant Code of Conduct
 600      - Various improvements in dict<> and pool<>
 601      - Added hashlib::mfp and refactored SigMap
 602      - Improved support for reals as module parameters
 603      - Various improvements in SMT2 back-end
 604      - Added "keep_hierarchy" attribute
 605      - Verilog front-end: define `BLACKBOX in -lib mode
 606      - Added API for converting internal cells to AIGs
 607      - Added ENABLE_LIBYOSYS Makefile option
 608      - Removed "techmap -share_map" (use "-map +/filename" instead)
 609      - Switched all Python scripts to Python 3
 610      - Added support for $display()/$write() and $finish() to Verilog front-end
 611      - Added "yosys-smtbmc" formal verification flow
 612      - Added options for clang sanitizers to Makefile
 613
 614  * New commands and options
 615      - Added "scc -expect <N> -nofeedback"
 616      - Added "proc_dlatch"
 617      - Added "check"
 618      - Added "select %xe %cie %coe %M %C %R"
 619      - Added "sat -dump_json" (WaveJSON format)
 620      - Added "sat -tempinduct-baseonly -tempinduct-inductonly"
 621      - Added "sat -stepsize" and "sat -tempinduct-step"
 622      - Added "sat -show-regs -show-public -show-all"
 623      - Added "write_json" (Native Yosys JSON format)
 624      - Added "write_blif -attr"
 625      - Added "dffinit"
 626      - Added "chparam"
 627      - Added "muxcover"
 628      - Added "pmuxtree"
 629      - Added memory_bram "make_outreg" feature
 630      - Added "splice -wires"
 631      - Added "dff2dffe -direct-match"
 632      - Added simplemap $lut support
 633      - Added "read_blif"
 634      - Added "opt_share -share_all"
 635      - Added "aigmap"
 636      - Added "write_smt2 -mem -regs -wires"
 637      - Added "memory -nordff"
 638      - Added "write_smv"
 639      - Added "synth -nordff -noalumacc"
 640      - Added "rename -top new_name"
 641      - Added "opt_const -clkinv"
 642      - Added "synth -nofsm"
 643      - Added "miter -assert"
 644      - Added "read_verilog -noautowire"
 645      - Added "read_verilog -nodpi"
 646      - Added "tribuf"
 647      - Added "lut2mux"
 648      - Added "nlutmap"
 649      - Added "qwp"
 650      - Added "test_cell -noeval"
 651      - Added "edgetypes"
 652      - Added "equiv_struct"
 653      - Added "equiv_purge"
 654      - Added "equiv_mark"
 655      - Added "equiv_add -try -cell"
 656      - Added "singleton"
 657      - Added "abc -g -luts"
 658      - Added "torder"
 659      - Added "write_blif -cname"
 660      - Added "submod -copy"
 661      - Added "dffsr2dff"
 662      - Added "stat -liberty"
 663
 664  * Synthesis metacommands
 665      - Various improvements in synth_xilinx
 666      - Added synth_ice40 and synth_greenpak4
 667      - Added "prep" metacommand for "synthesis lite"
 668
 669  * Cell library changes
 670      - Added cell types to "help" system
 671      - Added $meminit cell type
 672      - Added $assume cell type
 673      - Added $_MUX4_, $_MUX8_, and $_MUX16_ cells
 674      - Added $tribuf and $_TBUF_ cell types
 675      - Added read-enable to memory model
 676
 677  * YosysJS
 678      - Various improvements in emscripten build
 679      - Added alternative webworker-based JS API
 680      - Added a few example applications
 681
 682
 683 Yosys 0.4 .. Yosys 0.5
 684 ----------------------
 685
 686  * API changes
 687      - Added log_warning()
 688      - Added eval_select_args() and eval_select_op()
 689      - Added cell->known(), cell->input(portname), cell->output(portname)
 690      - Skip blackbox modules in design->selected_modules()
 691      - Replaced std::map<> and std::set<> with dict<> and pool<>
 692      - New SigSpec::extend() is what used to be SigSpec::extend_u0()
 693      - Added YS_OVERRIDE, YS_FINAL, YS_ATTRIBUTE, YS_NORETURN
 694
 695  * Cell library changes
 696      - Added flip-flops with enable ($dffe etc.)
 697      - Added $equiv cells for equivalence checking framework
 698
 699  * Various
 700      - Updated ABC to hg rev 61ad5f908c03
 701      - Added clock domain partitioning to ABC pass
 702      - Improved plugin building (see "yosys-config --build")
 703      - Added ENABLE_NDEBUG Makefile flag for high-performance builds
 704      - Added "yosys -d", "yosys -L" and other driver improvements
 705      - Added support for multi-bit (array) cell ports to "write_edif"
 706      - Now printing most output to stdout, not stderr
 707      - Added "onehot" attribute (set by "fsm_map")
 708      - Various performance improvements
 709      - Vastly improved Xilinx flow
 710      - Added "make unsintall"
 711
 712  * Equivalence checking
 713      - Added equivalence checking commands:
 714          equiv_make equiv_simple equiv_status
 715          equiv_induct equiv_miter
 716          equiv_add equiv_remove
 717
 718  * Block RAM support:
 719      - Added "memory_bram" command
 720      - Added BRAM support to Xilinx flow
 721
 722  * Other New Commands and Options
 723      - Added "dff2dffe"
 724      - Added "fsm -encfile"
 725      - Added "dfflibmap -prepare"
 726      - Added "write_blid -unbuf -undef -blackbox"
 727      - Added "write_smt2" for writing SMT-LIBv2 files
 728      - Added "test_cell -w -muxdiv"
 729      - Added "select -read"
 730
 731
 732 Yosys 0.3.0 .. Yosys 0.4
 733 ------------------------
 734
 735  * Platform Support
 736      - Added support for mxe-based cross-builds for win32
 737      - Added sourcecode-export as VisualStudio project
 738      - Added experimental EMCC (JavaScript) support
 739
 740  * Verilog Frontend
 741      - Added -sv option for SystemVerilog (and automatic *.sv file support)
 742      - Added support for real-valued constants and constant expressions
 743      - Added support for non-standard "via_celltype" attribute on task/func
 744      - Added support for non-standard "module mod_name(...);" syntax
 745      - Added support for non-standard """ macro bodies
 746      - Added support for array with more than one dimension
 747      - Added support for $readmemh and $readmemb
 748      - Added support for DPI functions
 749
 750  * Changes in internal cell library
 751      - Added $shift and $shiftx cell types
 752      - Added $alu, $lcu, $fa and $macc cell types
 753      - Removed $bu0 and $safe_pmux cell types
 754      - $mem/$memwr WR_EN input is now a per-data-bit enable signal
 755      - Added $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
 756      - Renamed ports of $lut cells (from I->O to A->Y)
 757      - Renamed $_INV_ to $_NOT_
 758
 759  * Changes for simple synthesis flows
 760      - There is now a "synth" command with a recommended default script
 761      - Many improvements in synthesis of arithmetic functions to gates
 762          - Multipliers and adders with many operands are using carry-save adder trees
 763          - Remaining adders are now implemented using Brent-Kung carry look-ahead adders
 764      - Various new high-level optimizations on RTL netlist
 765      - Various improvements in FSM optimization
 766      - Updated ABC to hg 5b5af75f1dda (from 2014-11-07)
 767
 768  * Changes in internal APIs and RTLIL
 769      - Added log_id() and log_cell() helper functions
 770      - Added function-like cell creation helpers
 771      - Added GetSize() function (like .size() but with int)
 772      - Major refactoring of RTLIL::Module and related classes
 773      - Major refactoring of RTLIL::SigSpec and related classes
 774      - Now RTLIL::IdString is essentially an int
 775      - Added macros for code coverage counters
 776      - Added some Makefile magic for pretty make logs
 777      - Added "kernel/yosys.h" with all the core definitions
 778      - Changed a lot of code from FILE* to c++ streams
 779      - Added RTLIL::Monitor API and "trace" command
 780      - Added "Yosys" C++ namespace
 781
 782  * Changes relevant to SAT solving
 783      - Added ezSAT::keep_cnf() and ezSAT::non_incremental()
 784      - Added native ezSAT support for vector shift ops
 785      - Updated MiniSAT to git 37dc6c67e2 (from 2013-09-25)
 786
 787  * New commands (or large improvements to commands)
 788      - Added "synth" command with default script
 789      - Added "share" (finally some real resource sharing)
 790      - Added "memory_share" (reduce number of ports on memories)
 791      - Added "wreduce" and "alumacc" commands
 792      - Added "opt -keepdc -fine -full -fast"
 793      - Added some "test_*" commands
 794
 795  * Various other changes
 796      - Added %D and %c select operators
 797      - Added support for labels in yosys scripts
 798      - Added support for here-documents in yosys scripts
 799      - Support "+/" prefix for files from proc_share_dir
 800      - Added "autoidx" statement to ilang language
 801      - Switched from "yosys-svgviewer" to "xdot"
 802      - Renamed "stdcells.v" to "techmap.v"
 803      - Various bug fixes and small improvements
 804      - Improved welcome and bye messages
 805
 806
 807 Yosys 0.2.0 .. Yosys 0.3.0
 808 --------------------------
 809
 810  * Driver program and overall behavior:
 811      - Added "design -push" and "design -pop"
 812      - Added "tee" command for redirecting log output
 813
 814  * Changes in the internal cell library:
 815      - Added $dlatchsr and $_DLATCHSR_???_ cell types
 816
 817  * Improvements in Verilog frontend:
 818      - Improved support for const functions (case, always, repeat)
 819      - The generate..endgenerate keywords are now optional
 820      - Added support for arrays of module instances
 821      - Added support for "`default_nettype" directive
 822      - Added support for "`line" directive
 823
 824  * Other front- and back-ends:
 825      - Various changes to "write_blif" options
 826      - Various improvements in EDIF backend
 827      - Added "vhdl2verilog" pseudo-front-end
 828      - Added "verific" pseudo-front-end
 829
 830  * Improvements in technology mapping:
 831      - Added support for recursive techmap
 832      - Added CONSTMSK and CONSTVAL features to techmap
 833      - Added _TECHMAP_CONNMAP_*_ feature to techmap
 834      - Added _TECHMAP_REPLACE_ feature to techmap
 835      - Added "connwrappers" command for wrap-extract-unwrap method
 836      - Added "extract -map %<design_name>" feature
 837      - Added "extract -ignore_param ..." and "extract -ignore_parameters"
 838      - Added "techmap -max_iter" option
 839
 840  * Improvements to "eval" and "sat" framework:
 841      - Now include a copy of Minisat (with build fixes applied)
 842      - Switched to Minisat::SimpSolver as SAT back-end
 843      - Added "sat -dump_vcd" feature
 844      - Added "sat -dump_cnf" feature
 845      - Added "sat -initsteps <N>" feature
 846      - Added "freduce -stop <N>" feature
 847      - Added "freduce -dump <prefix>" feature
 848
 849  * Integration with ABC:
 850      - Updated ABC rev to 7600ffb9340c
 851
 852  * Improvements in the internal APIs:
 853      - Added RTLIL::Module::add... helper methods
 854      - Various build fixes for OSX (Darwin) and OpenBSD
 855
 856
 857 Yosys 0.1.0 .. Yosys 0.2.0
 858 --------------------------
 859
 860  * Changes to the driver program:
 861      - Added "yosys -h" and "yosys -H"
 862      - Added support for backslash line continuation in scripts
 863      - Added support for #-comments in same line as command
 864      - Added "echo" and "log" commands
 865
 866  * Improvements in Verilog frontend:
 867      - Added support for local registers in named blocks
 868      - Added support for "case" in "generate" blocks
 869      - Added support for $clog2 system function
 870      - Added support for basic SystemVerilog assert statements
 871      - Added preprocessor support for macro arguments
 872      - Added preprocessor support for `elsif statement
 873      - Added "verilog_defaults" command
 874      - Added read_verilog -icells option
 875      - Added support for constant sizes from parameters
 876      - Added "read_verilog -setattr"
 877      - Added support for function returning 'integer'
 878      - Added limited support for function calls in parameter values
 879      - Added "read_verilog -defer" to suppress evaluation of modules with default parameters
 880
 881  * Other front- and back-ends:
 882      - Added BTOR backend
 883      - Added Liberty frontend
 884
 885  * Improvements in technology mapping:
 886      - The "dfflibmap" command now strongly prefers solutions with
 887            no inverters in clock paths
 888      - The "dfflibmap" command now prefers cells with smaller area
 889      - Added support for multiple -map options to techmap
 890      - Added "dfflibmap" support for //-comments in liberty files
 891      - Added "memory_unpack" command to revert "memory_collect"
 892      - Added standard techmap rule "techmap -share_map pmux2mux.v"
 893      - Added "iopadmap -bits"
 894      - Added "setundef" command
 895      - Added "hilomap" command
 896
 897  * Changes in the internal cell library:
 898      - Major rewrite of simlib.v for better compatibility with other tools
 899      - Added PRIORITY parameter to $memwr cells
 900      - Added TRANSPARENT parameter to $memrd cells
 901      - Added RD_TRANSPARENT parameter to $mem cells
 902      - Added $bu0 cell (always 0-extend, even undef MSB)
 903      - Added $assert cell type
 904      - Added $slice and $concat cell types
 905
 906  * Integration with ABC:
 907      - Updated ABC to hg rev 2058c8ccea68
 908      - Tighter integration of ABC build with Yosys build. The make
 909            targets 'make abc' and 'make install-abc' are now obsolete.
 910      - Added support for passing FFs from one clock domain through ABC
 911      - Now always use BLIF as exchange format with ABC
 912      - Added support for "abc -script +<command_sequence>"
 913      - Improved standard ABC recipe
 914      - Added support for "keep" attribute to abc command
 915      - Added "abc -dff / -clk / -keepff" options
 916
 917  * Improvements to "eval" and "sat" framework:
 918      - Added support for "0" and "~0" in right-hand side -set expressions
 919      - Added "eval -set-undef" and "eval -table"
 920      - Added "sat -set-init" and "sat -set-init-*" for sequential problems
 921      - Added undef support to SAT solver, incl. various new "sat" options
 922      - Added correct support for === and !== for "eval" and "sat"
 923      - Added "sat -tempinduct" (default -seq is now non-induction sequential)
 924      - Added "sat -prove-asserts"
 925      - Complete rewrite of the 'freduce' command
 926      - Added "miter" command
 927      - Added "sat -show-inputs" and "sat -show-outputs"
 928      - Added "sat -ignore_unknown_cells" (now produce an error by default)
 929      - Added "sat -falsify"
 930      - Now "sat -verify" and "sat -falsify" can also be used without "-prove"
 931      - Added "expose" command
 932      - Added support for @<sel_name> to sat and eval signal expressions
 933
 934  * Changes in the 'make test' framework and auxiliary test tools:
 935      - Added autotest.sh -p and -f options
 936      - Replaced autotest.sh ISIM support with XSIM support
 937      - Added test cases for SAT framework
 938
 939  * Added "abbreviated IDs":
 940      - Now $<something>$foo can be abbreviated as $foo.
 941      - Usually this last part is a unique id (from RTLIL::autoidx)
 942      - This abbreviated IDs are now also used in "show" output
 943
 944  * Other changes to selection framework:
 945      - Now */ is optional in */<mode>:<arg> expressions
 946      - Added "select -assert-none" and "select -assert-any"
 947      - Added support for matching modules by attribute (A:<expr>)
 948      - Added "select -none"
 949      - Added support for r:<expr> pattern for matching cell parameters
 950      - Added support for !=, <, <=, >=, > for attribute and parameter matching
 951      - Added support for %s for selecting sub-modules
 952      - Added support for %m for expanding selections to whole modules
 953      - Added support for i:*, o:* and x:* pattern for selecting module ports
 954      - Added support for s:<expr> pattern for matching wire width
 955      - Added support for %a operation to select wire aliases
 956
 957  * Various other changes to commands and options:
 958      - The "ls" command now supports wildcards
 959      - Added "show -pause" and "show -format dot"
 960      - Added "show -color" support for cells
 961      - Added "show -label" and "show -notitle"
 962      - Added "dump -m" and "dump -n"
 963      - Added "history" command
 964      - Added "rename -hide"
 965      - Added "connect" command
 966      - Added "splitnets -driver"
 967      - Added "opt_const -mux_undef"
 968      - Added "opt_const -mux_bool"
 969      - Added "opt_const -undriven"
 970      - Added "opt -mux_undef -mux_bool -undriven -purge"
 971      - Added "hierarchy -libdir"
 972      - Added "hierarchy -purge_lib" (by default now do not remove lib cells)
 973      - Added "delete" command
 974      - Added "dump -append"
 975      - Added "setattr" and "setparam" commands
 976      - Added "design -stash/-copy-from/-copy-to"
 977      - Added "copy" command
 978      - Added "splice" command
 979