CHANGELOG

   1
   2 List of major changes and improvements between releases
   3 =======================================================
   4
   5 Yosys 0.11 .. Yosys 0.12
   6 --------------------------
   7
   8  * Various
   9     - Added iopadmap native support for negative-polarity output enable
  10     - ABC update
  11
  12  * SystemVerilog
  13     - Support parameters using struct as a wiretype
  14
  15  * New commands and options
  16     - Added "-genlib" option to "abc" pass
  17     - Added "sta" very crude static timing analysis pass
  18
  19  * Verific support
  20     - Fixed memory block size in import
  21
  22  * New back-ends
  23     - Added support for GateMate FPGA from Cologne Chip AG
  24
  25  * Intel ALM support
  26     - Added preliminary Arria V support
  27
  28
  29 Yosys 0.10 .. Yosys 0.11
  30 --------------------------
  31
  32  * Various
  33     - Added $aldff and $aldffe (flip-flops with async load) cells
  34
  35  * SystemVerilog
  36     - Fixed an issue which prevented writing directly to a memory word via a
  37       connection to an output port
  38     - Fixed an issue which prevented unbased unsized literals (e.g., `'1`) from
  39       filling the width of a cell input
  40     - Fixed an issue where connecting a slice covering the entirety of a signed
  41       signal to a cell input would cause a failed assertion
  42
  43  * Verific support
  44     - Importer support for {PRIM,WIDE_OPER}_DFF
  45     - Importer support for PRIM_BUFIF1
  46     - Option to use Verific without VHDL support
  47     - Importer support for {PRIM,WIDE_OPER}_DLATCH{,RS}
  48     - Added -cfg option for getting/setting Verific runtime flags
  49
  50 Yosys 0.9 .. Yosys 0.10
  51 --------------------------
  52
  53  * Various
  54     - Added automatic gzip decompression for frontends
  55     - Added $_NMUX_ cell type
  56     - Added automatic gzip compression (based on filename extension) for backends
  57     - Improve attribute and parameter encoding in JSON to avoid ambiguities between
  58       bit vectors and strings containing [01xz]*
  59     - Improvements in pmgen: subpattern and recursive matches
  60     - Support explicit FIRRTL properties
  61     - Improvements in pmgen: slices, choices, define, generate
  62     - Added "_TECHMAP_WIREINIT_*_" parameter and "_TECHMAP_REMOVEINIT_*_" wire for "techmap" pass
  63     - Added +/mul2dsp.v for decomposing wide multipliers to custom-sized ones
  64     - Added new frontend: rpc
  65     - Added --version and -version as aliases for -V
  66     - Improve yosys-smtbmc "solver not found" handling
  67     - Improved support of $readmem[hb] Memory Content File inclusion
  68     - Added CXXRTL backend
  69     - Use YosysHQ/abc instead of upstream berkeley-abc/abc
  70     - Added WASI platform support.
  71     - Added extmodule support to firrtl backend
  72     - Added $divfloor and $modfloor cells
  73     - Added $adffe, $dffsre, $sdff, $sdffe, $sdffce, $adlatch cells
  74     - Added "_TECHMAP_CELLNAME_" parameter for "techmap" pass
  75     - Added firrtl backend support for generic parameters in blackbox components
  76     - Added $meminit_v2 cells (with support for write mask)
  77     - Added $mem_v2, $memrd_v2, $memwr_v2, with the following features:
  78       - write priority masks, per write/write port pair
  79       - transparency and undefined collision behavior masks, per read/write port pair
  80       - read port reset and initialization
  81       - wide ports (accessing a naturally aligned power-of-two number of memory cells)
  82
  83  * New commands and options
  84     - Added "write_xaiger" backend
  85     - Added "read_xaiger"
  86     - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only)
  87     - Added "synth -abc9" (experimental)
  88     - Added "script -scriptwire"
  89     - Added "clkbufmap" pass
  90     - Added "extractinv" pass and "invertible_pin" attribute
  91     - Added "proc_clean -quiet"
  92     - Added "proc_prune" pass
  93     - Added "stat -tech cmos"
  94     - Added "opt_share" pass, run as part of "opt -full"
  95     - Added "-match-init" option to "dff2dffs" pass
  96     - Added "equiv_opt -multiclock"
  97     - Added "techmap_autopurge" support to techmap
  98     - Added "add -mod <modname[s]>"
  99     - Added "paramap" pass
 100     - Added "portlist" command
 101     - Added "check -mapped"
 102     - Added "check -allow-tbuf"
 103     - Added "autoname" pass
 104     - Added "write_verilog -extmem"
 105     - Added "opt_mem" pass
 106     - Added "scratchpad" pass
 107     - Added "fminit" pass
 108     - Added "opt_lut_ins" pass
 109     - Added "logger" pass
 110     - Added "show -nobg"
 111     - Added "exec" command
 112     - Added "design -delete"
 113     - Added "design -push-copy"
 114     - Added "qbfsat" command
 115     - Added "select -unset"
 116     - Added "dfflegalize" pass
 117     - Removed "opt_expr -clkinv" option, made it the default
 118     - Added "proc -nomux
 119     - Merged "dffsr2dff", "opt_rmdff", "dff2dffe", "dff2dffs", "peepopt.dffmux" passes into a new "opt_dff" pass
 120
 121  * SystemVerilog
 122     - Added checking of always block types (always_comb, always_latch and always_ff)
 123     - Added support for wildcard port connections (.*)
 124     - Added support for enum typedefs
 125     - Added support for structs and packed unions.
 126     - Allow constant function calls in for loops and generate if and case
 127     - Added support for static cast
 128     - Added support for logic typed parameters
 129     - Fixed generate scoping issues
 130     - Added support for real-valued parameters
 131     - Allow localparams in constant functions
 132     - Module name scope support
 133     - Support recursive functions using ternary expressions
 134     - Extended support for integer types
 135     - Support for parameters without default values
 136     - Allow globals in one file to depend on globals in another
 137     - Added support for: *=, /=, %=, <<=, >>=, <<<=, >>>=
 138     - Added support for parsing the 'bind' construct
 139     - support declaration in procedural for initialization
 140     - support declaration in generate for initialization
 141     - Support wand and wor of data types
 142
 143  * Verific support
 144     - Added "verific -L"
 145     - Add Verific SVA support for "always" properties
 146     - Add Verific support for SVA nexttime properties
 147     - Improve handling of verific primitives in "verific -import -V" mode
 148     - Import attributes for wires
 149     - Support VHDL enums
 150     - Added support for command files
 151
 152  * New back-ends
 153     - Added initial EFINIX support
 154     - Added Intel ALM: alternative synthesis for Intel FPGAs
 155     - Added initial Nexus support
 156     - Added initial MachXO2 support
 157     - Added initial QuickLogic PolarPro 3 support
 158
 159  * ECP5 support
 160     - Renamed labels/options in synth_ecp5 (e.g. dram -> map_lutram; -nodram -> -nolutram)
 161     - Added "synth_ecp5 -abc9" (experimental)
 162     - Added "synth_ecp5 -nowidelut"
 163     - "synth_ecp5" to now infer DSP blocks (-nodsp to disable, experimental)
 164
 165  * iCE40 support
 166     - Added "synth_ice40 -abc9" (experimental)
 167     - Added "synth_ice40 -device"
 168     - Renamed labels/options in synth_ice40 (e.g. dram -> map_lutram; -nodram -> -nolutram)
 169     - Added "ice40_wrapcarry" to encapsulate SB_LUT+SB_CARRY pairs for techmapping
 170     - Removed "ice40_unlut"
 171     - Added "ice40_dsp" for Lattice iCE40 DSP packing
 172     - "synth_ice40 -dsp" to infer DSP blocks
 173
 174  * Xilinx support
 175     - Added "synth_xilinx -abc9" (experimental)
 176     - Added "synth_xilinx -nocarry"
 177     - Added "synth_xilinx -nowidelut"
 178     - "synth_xilinx" to now infer wide multiplexers (-widemux <min> to enable)
 179     - Renamed labels/options in synth_xilinx (e.g. dram -> map_lutram; -nodram -> -nolutram)
 180     - Added "synth_xilinx -family xc6s" for Spartan 6 support (experimental)
 181     - Added "synth_xilinx -ise" (experimental)
 182     - Added "synth_xilinx -iopad"
 183     - "synth_xilinx" now automatically inserts clock buffers (add -noclkbuf to disable)
 184     - Added "xilinx_srl" for Xilinx shift register extraction
 185     - Removed "shregmap -tech xilinx" (superseded by "xilinx_srl")
 186     - Added "xilinx_dsp" for Xilinx DSP packing
 187     - "synth_xilinx" to now infer DSP blocks (-nodsp to disable)
 188     - Added latch support to synth_xilinx
 189     - Added support for flip-flops with synchronous reset to synth_xilinx
 190     - Added support for flip-flops with reset and enable to synth_xilinx
 191     - Added "xilinx_dffopt" pass
 192     - Added "synth_xilinx -dff"
 193
 194  * Intel support
 195     - Renamed labels in synth_intel (e.g. bram -> map_bram)
 196     - synth_intel: cyclone10 -> cyclone10lp, a10gx -> arria10gx
 197     - Added "intel_alm -abc9" (experimental)
 198
 199  * CoolRunner2 support
 200     - Separate and improve buffer cell insertion pass
 201     - Use extract_counter to optimize counters
 202
 203 Yosys 0.8 .. Yosys 0.9
 204 ----------------------
 205
 206  * Various
 207     - Many bugfixes and small improvements
 208     - Added support for SystemVerilog interfaces and modports
 209     - Added "write_edif -attrprop"
 210     - Added "opt_lut" pass
 211     - Added "gate2lut.v" techmap rule
 212     - Added "rename -src"
 213     - Added "equiv_opt" pass
 214     - Added "flowmap" LUT mapping pass
 215     - Added "rename -wire" to rename cells based on the wires they drive
 216     - Added "bugpoint" for creating minimised testcases
 217     - Added "write_edif -gndvccy"
 218     - "write_verilog" to escape Verilog keywords
 219     - Fixed sign handling of real constants
 220     - "write_verilog" to write initial statement for initial flop state
 221     - Added pmgen pattern matcher generator
 222     - Fixed opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_
 223     - Added "setundef -params" to replace undefined cell parameters
 224     - Renamed "yosys -D" to "yosys -U", added "yosys -D" to set Verilog defines
 225     - Fixed handling of defparam when default_nettype is none
 226     - Fixed "wreduce" flipflop handling
 227     - Fixed FIRRTL to Verilog process instance subfield assignment
 228     - Added "write_verilog -siminit"
 229     - Several fixes and improvements for mem2reg memories
 230     - Fixed handling of task output ports in clocked always blocks
 231     - Improved handling of and-with-1 and or-with-0 in "opt_expr"
 232     - Added "read_aiger" frontend
 233     - Added "mutate" pass
 234     - Added "hdlname" attribute
 235     - Added "rename -output"
 236     - Added "read_ilang -lib"
 237     - Improved "proc" full_case detection and handling
 238     - Added "whitebox" and "lib_whitebox" attributes
 239     - Added "read_verilog -nowb", "flatten -wb" and "wbflip"
 240     - Added Python bindings and support for Python plug-ins
 241     - Added "pmux2shiftx"
 242     - Added log_debug framework for reduced default verbosity
 243     - Improved "opt_expr" and "opt_clean" handling of (partially) undriven and/or unused wires
 244     - Added "peepopt" peephole optimisation pass using pmgen
 245     - Added approximate support for SystemVerilog "var" keyword
 246     - Added parsing of "specify" blocks into $specrule and $specify[23]
 247     - Added support for attributes on parameters and localparams
 248     - Added support for parsing attributes on port connections
 249     - Added "wreduce -keepdc"
 250     - Added support for optimising $dffe and $_DFFE_* cells in "opt_rmdff"
 251     - Added Verilog wand/wor wire type support
 252     - Added support for elaboration system tasks
 253     - Added "muxcover -mux{4,8,16}=<cost>"
 254     - Added "muxcover -dmux=<cost>"
 255     - Added "muxcover -nopartial"
 256     - Added "muxpack" pass
 257     - Added "pmux2shiftx -norange"
 258     - Added support for "~" in filename parsing
 259     - Added "read_verilog -pwires" feature to turn parameters into wires
 260     - Fixed sign extension of unsized constants with 'bx and 'bz MSB
 261     - Fixed genvar to be a signed type
 262     - Added support for attributes on case rules
 263     - Added "upto" and "offset" to JSON frontend and backend
 264     - Several liberty file parser improvements
 265     - Fixed handling of more complex BRAM patterns
 266     - Add "write_aiger -I -O -B"
 267
 268  * Formal Verification
 269     - Added $changed support to read_verilog
 270     - Added "read_verilog -noassert -noassume -assert-assumes"
 271     - Added btor ops for $mul, $div, $mod and $concat
 272     - Added yosys-smtbmc support for btor witnesses
 273     - Added "supercover" pass
 274     - Fixed $global_clock handling vs autowire
 275     - Added $dffsr support to "async2sync"
 276     - Added "fmcombine" pass
 277     - Added memory init support in "write_btor"
 278     - Added "cutpoint" pass
 279     - Changed "ne" to "neq" in btor2 output
 280     - Added support for SVA "final" keyword
 281     - Added "fmcombine -initeq -anyeq"
 282     - Added timescale and generated-by header to yosys-smtbmc vcd output
 283     - Improved BTOR2 handling of undriven wires
 284
 285  * Verific support
 286     - Enabled Verific flags vhdl_support_variable_slice and veri_elaborate_top_level_modules_having_interface_ports
 287     - Improved support for asymmetric memories
 288     - Added "verific -chparam"
 289     - Fixed "verific -extnets" for more complex situations
 290     - Added "read -verific" and "read -noverific"
 291     - Added "hierarchy -chparam"
 292
 293  * New back-ends
 294     - Added initial Anlogic support
 295     - Added initial SmartFusion2 and IGLOO2 support
 296
 297  * ECP5 support
 298     - Added "synth_ecp5 -nowidelut"
 299     - Added BRAM inference support to "synth_ecp5"
 300     - Added support for transforming Diamond IO and flipflop primitives
 301
 302  * iCE40 support
 303     - Added "ice40_unlut" pass
 304     - Added "synth_ice40 -relut"
 305     - Added "synth_ice40 -noabc"
 306     - Added "synth_ice40 -dffe_min_ce_use"
 307     - Added DSP inference support using pmgen
 308     - Added support for initialising BRAM primitives from a file
 309     - Added iCE40 Ultra RGB LED driver cells
 310
 311  * Xilinx support
 312     - Use "write_edif -pvector bra" for Xilinx EDIF files
 313     - Fixes for VPR place and route support with "synth_xilinx"
 314     - Added more cell simulation models
 315     - Added "synth_xilinx -family"
 316     - Added "stat -tech xilinx" to estimate logic cell usage
 317     - Added "synth_xilinx -nocarry"
 318     - Added "synth_xilinx -nowidelut"
 319     - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
 320     - Added support for mapping RAM32X1D
 321
 322 Yosys 0.7 .. Yosys 0.8
 323 ----------------------
 324
 325  * Various
 326     - Many bugfixes and small improvements
 327     - Strip debug symbols from installed binary
 328     - Replace -ignore_redef with -[no]overwrite in front-ends
 329     - Added write_verilog hex dump support, add -nohex option
 330     - Added "write_verilog -decimal"
 331     - Added "scc -set_attr"
 332     - Added "verilog_defines" command
 333     - Remember defines from one read_verilog to next
 334     - Added support for hierarchical defparam
 335     - Added FIRRTL back-end
 336     - Improved ABC default scripts
 337     - Added "design -reset-vlog"
 338     - Added "yosys -W regex", "yosys -w regex", and "yosys -e regex"
 339     - Added Verilog $rtoi and $itor support
 340     - Added "check -initdrv"
 341     - Added "read_blif -wideports"
 342     - Added support for SystemVerilog "++" and "--" operators
 343     - Added support for SystemVerilog unique, unique0, and priority case
 344     - Added "write_edif" options for edif "flavors"
 345     - Added support for resetall compiler directive
 346     - Added simple C beck-end (bitwise combinatorical only atm)
 347     - Added $_ANDNOT_ and $_ORNOT_ cell types
 348     - Added cell library aliases to "abc -g"
 349     - Added "setundef -anyseq"
 350     - Added "chtype" command
 351     - Added "design -import"
 352     - Added "write_table" command
 353     - Added "read_json" command
 354     - Added "sim" command
 355     - Added "extract_fa" and "extract_reduce" commands
 356     - Added "extract_counter" command
 357     - Added "opt_demorgan" command
 358     - Added support for $size and $bits SystemVerilog functions
 359     - Added "blackbox" command
 360     - Added "ltp" command
 361     - Added support for editline as replacement for readline
 362     - Added warnings for driver-driver conflicts between FFs (and other cells) and constants
 363     - Added "yosys -E" for creating Makefile dependencies files
 364     - Added "synth -noshare"
 365     - Added "memory_nordff"
 366     - Added "setundef -undef -expose -anyconst"
 367     - Added "expose -input"
 368     - Added specify/specparam parser support (simply ignore them)
 369     - Added "write_blif -inames -iattr"
 370     - Added "hierarchy -simcheck"
 371     - Added an option to statically link abc into yosys
 372     - Added protobuf back-end
 373     - Added BLIF parsing support for .conn and .cname
 374     - Added read_verilog error checking for reg/wire/logic misuse
 375     - Added "make coverage" and ENABLE_GCOV build option
 376
 377  * Changes in Yosys APIs
 378     - Added ConstEval defaultval feature
 379     - Added {get,set}_src_attribute() methods on RTLIL::AttrObject
 380     - Added SigSpec::is_fully_ones() and Const::is_fully_ones()
 381     - Added log_file_warning() and log_file_error() functions
 382
 383  * Formal Verification
 384     - Added "write_aiger"
 385     - Added "yosys-smtbmc --aig"
 386     - Added "always <positive_int>" to .smtc format
 387     - Added $cover cell type and support for cover properties
 388     - Added $fair/$live cell type and support for liveness properties
 389     - Added smtbmc support for memory vcd dumping
 390     - Added "chformal" command
 391     - Added "write_smt2 -stbv" and "write_smt2 -stdt"
 392     - Fix equiv_simple, old behavior now available with "equiv_simple -short"
 393     - Change to Yices2 as default SMT solver (it is GPL now)
 394     - Added "yosys-smtbmc --presat" (now default in SymbiYosys)
 395     - Added "yosys-smtbmc --smtc-init --smtc-top --noinit"
 396     - Added a brand new "write_btor" command for BTOR2
 397     - Added clk2fflogic memory support and other improvements
 398     - Added "async memory write" support to write_smt2
 399     - Simulate clock toggling in yosys-smtbmc VCD output
 400     - Added $allseq/$allconst cells for EA-solving
 401     - Make -nordff the default in "prep"
 402     - Added (* gclk *) attribute
 403     - Added "async2sync" pass for single-clock designs with async resets
 404
 405  * Verific support
 406     - Many improvements in Verific front-end
 407     - Added proper handling of concurent SVA properties
 408     - Map "const" and "rand const" to $anyseq/$anyconst
 409     - Added "verific -import -flatten" and "verific -import -extnets"
 410     - Added "verific -vlog-incdir -vlog-define -vlog-libdir"
 411     - Remove PSL support (because PSL has been removed in upstream Verific)
 412     - Improve integration with "hierarchy" command design elaboration
 413     - Added YOSYS_NOVERIFIC for running non-verific test cases with verific bin
 414     - Added simpilied "read" command that automatically uses verific if available
 415     - Added "verific -set-<severity> <msg_id>.."
 416     - Added "verific -work <libname>"
 417
 418  * New back-ends
 419     - Added initial Coolrunner-II support
 420     - Added initial eASIC support
 421     - Added initial ECP5 support
 422
 423  * GreenPAK Support
 424     - Added support for GP_DLATCH, GP_SPI, GP_DCMx, GP_COUNTx, etc.
 425
 426  * iCE40 Support
 427     - Add "synth_ice40 -vpr"
 428     - Add "synth_ice40 -nodffe"
 429     - Add "synth_ice40 -json"
 430     - Add Support for UltraPlus cells
 431
 432  * MAX10 and Cyclone IV Support
 433     - Added initial version of metacommand "synth_intel".
 434     - Improved write_verilog command to produce VQM netlist for Quartus Prime.
 435     - Added support for MAX10 FPGA family synthesis.
 436     - Added support for Cyclone IV family synthesis.
 437     - Added example of implementation for DE2i-150 board.
 438     - Added example of implementation for MAX10 development kit.
 439     - Added LFSR example from Asic World.
 440     - Added "dffinit -highlow" for mapping to Intel primitives
 441
 442
 443 Yosys 0.6 .. Yosys 0.7
 444 ----------------------
 445
 446  * Various
 447     - Added "yosys -D" feature
 448     - Added support for installed plugins in $(DATDIR)/plugins/
 449     - Renamed opt_const to opt_expr
 450     - Renamed opt_share to opt_merge
 451     - Added "prep -flatten" and "synth -flatten"
 452     - Added "prep -auto-top" and "synth -auto-top"
 453     - Using "mfs" and "lutpack" in ABC lut mapping
 454     - Support for abstract modules in chparam
 455     - Cleanup abstract modules at end of "hierarchy -top"
 456     - Added tristate buffer support to iopadmap
 457     - Added opt_expr support for div/mod by power-of-two
 458     - Added "select -assert-min <N> -assert-max <N>"
 459     - Added "attrmvcp" pass
 460     - Added "attrmap" command
 461     - Added "tee +INT -INT"
 462     - Added "zinit" pass
 463     - Added "setparam -type"
 464     - Added "shregmap" pass
 465     - Added "setundef -init"
 466     - Added "nlutmap -assert"
 467     - Added $sop cell type and "abc -sop -I <num> -P <num>"
 468     - Added "dc2" to default ABC scripts
 469     - Added "deminout"
 470     - Added "insbuf" command
 471     - Added "prep -nomem"
 472     - Added "opt_rmdff -keepdc"
 473     - Added "prep -nokeepdc"
 474     - Added initial version of "synth_gowin"
 475     - Added "fsm_expand -full"
 476     - Added support for fsm_encoding="user"
 477     - Many improvements in GreenPAK4 support
 478     - Added black box modules for all Xilinx 7-series lib cells
 479     - Added synth_ice40 support for latches via logic loops
 480     - Fixed ice40_opt lut unmapping, added "ice40_opt -unlut"
 481
 482  * Build System
 483     - Added ABCEXTERNAL and ABCURL make variables
 484     - Added BINDIR, LIBDIR, and DATDIR make variables
 485     - Added PKG_CONFIG make variable
 486     - Added SEED make variable (for "make test")
 487     - Added YOSYS_VER_STR make variable
 488     - Updated min GCC requirement to GCC 4.8
 489     - Updated required Bison version to Bison 3.x
 490
 491  * Internal APIs
 492     - Added ast.h to exported headers
 493     - Added ScriptPass helper class for script-like passes
 494     - Added CellEdgesDatabase API
 495
 496  * Front-ends and Back-ends
 497     - Added filename glob support to all front-ends
 498     - Added avail (black-box) module params to ilang format
 499     - Added $display %m support
 500     - Added support for $stop Verilog system task
 501     - Added support for SystemVerilog packages
 502     - Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b}
 503     - Added support for "active high" and "active low" latches in read_blif and write_blif
 504     - Use init value "2" for all uninitialized FFs in BLIF back-end
 505     - Added "read_blif -sop"
 506     - Added "write_blif -noalias"
 507     - Added various write_blif options for VTR support
 508     - write_json: also write module attributes.
 509     - Added "write_verilog -nodec -nostr -defparam"
 510     - Added "read_verilog -norestrict -assume-asserts"
 511     - Added support for bus interfaces to "read_liberty -lib"
 512     - Added liberty parser support for types within cell decls
 513     - Added "write_verilog -renameprefix -v"
 514     - Added "write_edif -nogndvcc"
 515
 516  * Formal Verification
 517     - Support for hierarchical designs in smt2 back-end
 518     - Yosys-smtbmc: Support for hierarchical VCD dumping
 519     - Added $initstate cell type and vlog function
 520     - Added $anyconst and $anyseq cell types and vlog functions
 521     - Added printing of code loc of failed asserts to yosys-smtbmc
 522     - Added memory_memx pass, "memory -memx", and "prep -memx"
 523     - Added "proc_mux -ifx"
 524     - Added "yosys-smtbmc -g"
 525     - Deprecated "write_smt2 -regs" (by default on now)
 526     - Made "write_smt2 -bv -mem" default, added "write_smt2 -nobv -nomem"
 527     - Added support for memories to smtio.py
 528     - Added "yosys-smtbmc --dump-vlogtb"
 529     - Added "yosys-smtbmc --smtc --dump-smtc"
 530     - Added "yosys-smtbmc --dump-all"
 531     - Added assertpmux command
 532     - Added "yosys-smtbmc --unroll"
 533     - Added $past, $stable, $rose, $fell SVA functions
 534     - Added "yosys-smtbmc --noinfo and --dummy"
 535     - Added "yosys-smtbmc --noincr"
 536     - Added "yosys-smtbmc --cex <filename>"
 537     - Added $ff and $_FF_ cell types
 538     - Added $global_clock verilog syntax support for creating $ff cells
 539     - Added clk2fflogic
 540
 541
 542 Yosys 0.5 .. Yosys 0.6
 543 ----------------------
 544
 545  * Various
 546      - Added Contributor Covenant Code of Conduct
 547      - Various improvements in dict<> and pool<>
 548      - Added hashlib::mfp and refactored SigMap
 549      - Improved support for reals as module parameters
 550      - Various improvements in SMT2 back-end
 551      - Added "keep_hierarchy" attribute
 552      - Verilog front-end: define `BLACKBOX in -lib mode
 553      - Added API for converting internal cells to AIGs
 554      - Added ENABLE_LIBYOSYS Makefile option
 555      - Removed "techmap -share_map" (use "-map +/filename" instead)
 556      - Switched all Python scripts to Python 3
 557      - Added support for $display()/$write() and $finish() to Verilog front-end
 558      - Added "yosys-smtbmc" formal verification flow
 559      - Added options for clang sanitizers to Makefile
 560
 561  * New commands and options
 562      - Added "scc -expect <N> -nofeedback"
 563      - Added "proc_dlatch"
 564      - Added "check"
 565      - Added "select %xe %cie %coe %M %C %R"
 566      - Added "sat -dump_json" (WaveJSON format)
 567      - Added "sat -tempinduct-baseonly -tempinduct-inductonly"
 568      - Added "sat -stepsize" and "sat -tempinduct-step"
 569      - Added "sat -show-regs -show-public -show-all"
 570      - Added "write_json" (Native Yosys JSON format)
 571      - Added "write_blif -attr"
 572      - Added "dffinit"
 573      - Added "chparam"
 574      - Added "muxcover"
 575      - Added "pmuxtree"
 576      - Added memory_bram "make_outreg" feature
 577      - Added "splice -wires"
 578      - Added "dff2dffe -direct-match"
 579      - Added simplemap $lut support
 580      - Added "read_blif"
 581      - Added "opt_share -share_all"
 582      - Added "aigmap"
 583      - Added "write_smt2 -mem -regs -wires"
 584      - Added "memory -nordff"
 585      - Added "write_smv"
 586      - Added "synth -nordff -noalumacc"
 587      - Added "rename -top new_name"
 588      - Added "opt_const -clkinv"
 589      - Added "synth -nofsm"
 590      - Added "miter -assert"
 591      - Added "read_verilog -noautowire"
 592      - Added "read_verilog -nodpi"
 593      - Added "tribuf"
 594      - Added "lut2mux"
 595      - Added "nlutmap"
 596      - Added "qwp"
 597      - Added "test_cell -noeval"
 598      - Added "edgetypes"
 599      - Added "equiv_struct"
 600      - Added "equiv_purge"
 601      - Added "equiv_mark"
 602      - Added "equiv_add -try -cell"
 603      - Added "singleton"
 604      - Added "abc -g -luts"
 605      - Added "torder"
 606      - Added "write_blif -cname"
 607      - Added "submod -copy"
 608      - Added "dffsr2dff"
 609      - Added "stat -liberty"
 610
 611  * Synthesis metacommands
 612      - Various improvements in synth_xilinx
 613      - Added synth_ice40 and synth_greenpak4
 614      - Added "prep" metacommand for "synthesis lite"
 615
 616  * Cell library changes
 617      - Added cell types to "help" system
 618      - Added $meminit cell type
 619      - Added $assume cell type
 620      - Added $_MUX4_, $_MUX8_, and $_MUX16_ cells
 621      - Added $tribuf and $_TBUF_ cell types
 622      - Added read-enable to memory model
 623
 624  * YosysJS
 625      - Various improvements in emscripten build
 626      - Added alternative webworker-based JS API
 627      - Added a few example applications
 628
 629
 630 Yosys 0.4 .. Yosys 0.5
 631 ----------------------
 632
 633  * API changes
 634      - Added log_warning()
 635      - Added eval_select_args() and eval_select_op()
 636      - Added cell->known(), cell->input(portname), cell->output(portname)
 637      - Skip blackbox modules in design->selected_modules()
 638      - Replaced std::map<> and std::set<> with dict<> and pool<>
 639      - New SigSpec::extend() is what used to be SigSpec::extend_u0()
 640      - Added YS_OVERRIDE, YS_FINAL, YS_ATTRIBUTE, YS_NORETURN
 641
 642  * Cell library changes
 643      - Added flip-flops with enable ($dffe etc.)
 644      - Added $equiv cells for equivalence checking framework
 645
 646  * Various
 647      - Updated ABC to hg rev 61ad5f908c03
 648      - Added clock domain partitioning to ABC pass
 649      - Improved plugin building (see "yosys-config --build")
 650      - Added ENABLE_NDEBUG Makefile flag for high-performance builds
 651      - Added "yosys -d", "yosys -L" and other driver improvements
 652      - Added support for multi-bit (array) cell ports to "write_edif"
 653      - Now printing most output to stdout, not stderr
 654      - Added "onehot" attribute (set by "fsm_map")
 655      - Various performance improvements
 656      - Vastly improved Xilinx flow
 657      - Added "make unsintall"
 658
 659  * Equivalence checking
 660      - Added equivalence checking commands:
 661          equiv_make equiv_simple equiv_status
 662          equiv_induct equiv_miter
 663          equiv_add equiv_remove
 664
 665  * Block RAM support:
 666      - Added "memory_bram" command
 667      - Added BRAM support to Xilinx flow
 668
 669  * Other New Commands and Options
 670      - Added "dff2dffe"
 671      - Added "fsm -encfile"
 672      - Added "dfflibmap -prepare"
 673      - Added "write_blid -unbuf -undef -blackbox"
 674      - Added "write_smt2" for writing SMT-LIBv2 files
 675      - Added "test_cell -w -muxdiv"
 676      - Added "select -read"
 677
 678
 679 Yosys 0.3.0 .. Yosys 0.4
 680 ------------------------
 681
 682  * Platform Support
 683      - Added support for mxe-based cross-builds for win32
 684      - Added sourcecode-export as VisualStudio project
 685      - Added experimental EMCC (JavaScript) support
 686
 687  * Verilog Frontend
 688      - Added -sv option for SystemVerilog (and automatic *.sv file support)
 689      - Added support for real-valued constants and constant expressions
 690      - Added support for non-standard "via_celltype" attribute on task/func
 691      - Added support for non-standard "module mod_name(...);" syntax
 692      - Added support for non-standard """ macro bodies
 693      - Added support for array with more than one dimension
 694      - Added support for $readmemh and $readmemb
 695      - Added support for DPI functions
 696
 697  * Changes in internal cell library
 698      - Added $shift and $shiftx cell types
 699      - Added $alu, $lcu, $fa and $macc cell types
 700      - Removed $bu0 and $safe_pmux cell types
 701      - $mem/$memwr WR_EN input is now a per-data-bit enable signal
 702      - Added $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
 703      - Renamed ports of $lut cells (from I->O to A->Y)
 704      - Renamed $_INV_ to $_NOT_
 705
 706  * Changes for simple synthesis flows
 707      - There is now a "synth" command with a recommended default script
 708      - Many improvements in synthesis of arithmetic functions to gates
 709          - Multipliers and adders with many operands are using carry-save adder trees
 710          - Remaining adders are now implemented using Brent-Kung carry look-ahead adders
 711      - Various new high-level optimizations on RTL netlist
 712      - Various improvements in FSM optimization
 713      - Updated ABC to hg 5b5af75f1dda (from 2014-11-07)
 714
 715  * Changes in internal APIs and RTLIL
 716      - Added log_id() and log_cell() helper functions
 717      - Added function-like cell creation helpers
 718      - Added GetSize() function (like .size() but with int)
 719      - Major refactoring of RTLIL::Module and related classes
 720      - Major refactoring of RTLIL::SigSpec and related classes
 721      - Now RTLIL::IdString is essentially an int
 722      - Added macros for code coverage counters
 723      - Added some Makefile magic for pretty make logs
 724      - Added "kernel/yosys.h" with all the core definitions
 725      - Changed a lot of code from FILE* to c++ streams
 726      - Added RTLIL::Monitor API and "trace" command
 727      - Added "Yosys" C++ namespace
 728
 729  * Changes relevant to SAT solving
 730      - Added ezSAT::keep_cnf() and ezSAT::non_incremental()
 731      - Added native ezSAT support for vector shift ops
 732      - Updated MiniSAT to git 37dc6c67e2 (from 2013-09-25)
 733
 734  * New commands (or large improvements to commands)
 735      - Added "synth" command with default script
 736      - Added "share" (finally some real resource sharing)
 737      - Added "memory_share" (reduce number of ports on memories)
 738      - Added "wreduce" and "alumacc" commands
 739      - Added "opt -keepdc -fine -full -fast"
 740      - Added some "test_*" commands
 741
 742  * Various other changes
 743      - Added %D and %c select operators
 744      - Added support for labels in yosys scripts
 745      - Added support for here-documents in yosys scripts
 746      - Support "+/" prefix for files from proc_share_dir
 747      - Added "autoidx" statement to ilang language
 748      - Switched from "yosys-svgviewer" to "xdot"
 749      - Renamed "stdcells.v" to "techmap.v"
 750      - Various bug fixes and small improvements
 751      - Improved welcome and bye messages
 752
 753
 754 Yosys 0.2.0 .. Yosys 0.3.0
 755 --------------------------
 756
 757  * Driver program and overall behavior:
 758      - Added "design -push" and "design -pop"
 759      - Added "tee" command for redirecting log output
 760
 761  * Changes in the internal cell library:
 762      - Added $dlatchsr and $_DLATCHSR_???_ cell types
 763
 764  * Improvements in Verilog frontend:
 765      - Improved support for const functions (case, always, repeat)
 766      - The generate..endgenerate keywords are now optional
 767      - Added support for arrays of module instances
 768      - Added support for "`default_nettype" directive
 769      - Added support for "`line" directive
 770
 771  * Other front- and back-ends:
 772      - Various changes to "write_blif" options
 773      - Various improvements in EDIF backend
 774      - Added "vhdl2verilog" pseudo-front-end
 775      - Added "verific" pseudo-front-end
 776
 777  * Improvements in technology mapping:
 778      - Added support for recursive techmap
 779      - Added CONSTMSK and CONSTVAL features to techmap
 780      - Added _TECHMAP_CONNMAP_*_ feature to techmap
 781      - Added _TECHMAP_REPLACE_ feature to techmap
 782      - Added "connwrappers" command for wrap-extract-unwrap method
 783      - Added "extract -map %<design_name>" feature
 784      - Added "extract -ignore_param ..." and "extract -ignore_parameters"
 785      - Added "techmap -max_iter" option
 786
 787  * Improvements to "eval" and "sat" framework:
 788      - Now include a copy of Minisat (with build fixes applied)
 789      - Switched to Minisat::SimpSolver as SAT back-end
 790      - Added "sat -dump_vcd" feature
 791      - Added "sat -dump_cnf" feature
 792      - Added "sat -initsteps <N>" feature
 793      - Added "freduce -stop <N>" feature
 794      - Added "freduce -dump <prefix>" feature
 795
 796  * Integration with ABC:
 797      - Updated ABC rev to 7600ffb9340c
 798
 799  * Improvements in the internal APIs:
 800      - Added RTLIL::Module::add... helper methods
 801      - Various build fixes for OSX (Darwin) and OpenBSD
 802
 803
 804 Yosys 0.1.0 .. Yosys 0.2.0
 805 --------------------------
 806
 807  * Changes to the driver program:
 808      - Added "yosys -h" and "yosys -H"
 809      - Added support for backslash line continuation in scripts
 810      - Added support for #-comments in same line as command
 811      - Added "echo" and "log" commands
 812
 813  * Improvements in Verilog frontend:
 814      - Added support for local registers in named blocks
 815      - Added support for "case" in "generate" blocks
 816      - Added support for $clog2 system function
 817      - Added support for basic SystemVerilog assert statements
 818      - Added preprocessor support for macro arguments
 819      - Added preprocessor support for `elsif statement
 820      - Added "verilog_defaults" command
 821      - Added read_verilog -icells option
 822      - Added support for constant sizes from parameters
 823      - Added "read_verilog -setattr"
 824      - Added support for function returning 'integer'
 825      - Added limited support for function calls in parameter values
 826      - Added "read_verilog -defer" to suppress evaluation of modules with default parameters
 827
 828  * Other front- and back-ends:
 829      - Added BTOR backend
 830      - Added Liberty frontend
 831
 832  * Improvements in technology mapping:
 833      - The "dfflibmap" command now strongly prefers solutions with
 834            no inverters in clock paths
 835      - The "dfflibmap" command now prefers cells with smaller area
 836      - Added support for multiple -map options to techmap
 837      - Added "dfflibmap" support for //-comments in liberty files
 838      - Added "memory_unpack" command to revert "memory_collect"
 839      - Added standard techmap rule "techmap -share_map pmux2mux.v"
 840      - Added "iopadmap -bits"
 841      - Added "setundef" command
 842      - Added "hilomap" command
 843
 844  * Changes in the internal cell library:
 845      - Major rewrite of simlib.v for better compatibility with other tools
 846      - Added PRIORITY parameter to $memwr cells
 847      - Added TRANSPARENT parameter to $memrd cells
 848      - Added RD_TRANSPARENT parameter to $mem cells
 849      - Added $bu0 cell (always 0-extend, even undef MSB)
 850      - Added $assert cell type
 851      - Added $slice and $concat cell types
 852
 853  * Integration with ABC:
 854      - Updated ABC to hg rev 2058c8ccea68
 855      - Tighter integration of ABC build with Yosys build. The make
 856            targets 'make abc' and 'make install-abc' are now obsolete.
 857      - Added support for passing FFs from one clock domain through ABC
 858      - Now always use BLIF as exchange format with ABC
 859      - Added support for "abc -script +<command_sequence>"
 860      - Improved standard ABC recipe
 861      - Added support for "keep" attribute to abc command
 862      - Added "abc -dff / -clk / -keepff" options
 863
 864  * Improvements to "eval" and "sat" framework:
 865      - Added support for "0" and "~0" in right-hand side -set expressions
 866      - Added "eval -set-undef" and "eval -table"
 867      - Added "sat -set-init" and "sat -set-init-*" for sequential problems
 868      - Added undef support to SAT solver, incl. various new "sat" options
 869      - Added correct support for === and !== for "eval" and "sat"
 870      - Added "sat -tempinduct" (default -seq is now non-induction sequential)
 871      - Added "sat -prove-asserts"
 872      - Complete rewrite of the 'freduce' command
 873      - Added "miter" command
 874      - Added "sat -show-inputs" and "sat -show-outputs"
 875      - Added "sat -ignore_unknown_cells" (now produce an error by default)
 876      - Added "sat -falsify"
 877      - Now "sat -verify" and "sat -falsify" can also be used without "-prove"
 878      - Added "expose" command
 879      - Added support for @<sel_name> to sat and eval signal expressions
 880
 881  * Changes in the 'make test' framework and auxiliary test tools:
 882      - Added autotest.sh -p and -f options
 883      - Replaced autotest.sh ISIM support with XSIM support
 884      - Added test cases for SAT framework
 885
 886  * Added "abbreviated IDs":
 887      - Now $<something>$foo can be abbreviated as $foo.
 888      - Usually this last part is a unique id (from RTLIL::autoidx)
 889      - This abbreviated IDs are now also used in "show" output
 890
 891  * Other changes to selection framework:
 892      - Now */ is optional in */<mode>:<arg> expressions
 893      - Added "select -assert-none" and "select -assert-any"
 894      - Added support for matching modules by attribute (A:<expr>)
 895      - Added "select -none"
 896      - Added support for r:<expr> pattern for matching cell parameters
 897      - Added support for !=, <, <=, >=, > for attribute and parameter matching
 898      - Added support for %s for selecting sub-modules
 899      - Added support for %m for expanding selections to whole modules
 900      - Added support for i:*, o:* and x:* pattern for selecting module ports
 901      - Added support for s:<expr> pattern for matching wire width
 902      - Added support for %a operation to select wire aliases
 903
 904  * Various other changes to commands and options:
 905      - The "ls" command now supports wildcards
 906      - Added "show -pause" and "show -format dot"
 907      - Added "show -color" support for cells
 908      - Added "show -label" and "show -notitle"
 909      - Added "dump -m" and "dump -n"
 910      - Added "history" command
 911      - Added "rename -hide"
 912      - Added "connect" command
 913      - Added "splitnets -driver"
 914      - Added "opt_const -mux_undef"
 915      - Added "opt_const -mux_bool"
 916      - Added "opt_const -undriven"
 917      - Added "opt -mux_undef -mux_bool -undriven -purge"
 918      - Added "hierarchy -libdir"
 919      - Added "hierarchy -purge_lib" (by default now do not remove lib cells)
 920      - Added "delete" command
 921      - Added "dump -append"
 922      - Added "setattr" and "setparam" commands
 923      - Added "design -stash/-copy-from/-copy-to"
 924      - Added "copy" command
 925      - Added "splice" command
 926