CHANGELOG

   1
   2 List of major changes and improvements between releases
   3 =======================================================
   4
   5 Yosys 0.10 .. Yosys 0.10-dev
   6 --------------------------
   7
   8
   9 Yosys 0.9 .. Yosys 0.10
  10 --------------------------
  11
  12  * Various
  13     - Added automatic gzip decompression for frontends
  14     - Added $_NMUX_ cell type
  15     - Added automatic gzip compression (based on filename extension) for backends
  16     - Improve attribute and parameter encoding in JSON to avoid ambiguities between
  17       bit vectors and strings containing [01xz]*
  18     - Improvements in pmgen: subpattern and recursive matches
  19     - Support explicit FIRRTL properties
  20     - Improvements in pmgen: slices, choices, define, generate
  21     - Added "_TECHMAP_WIREINIT_*_" parameter and "_TECHMAP_REMOVEINIT_*_" wire for "techmap" pass
  22     - Added +/mul2dsp.v for decomposing wide multipliers to custom-sized ones
  23     - Added new frontend: rpc
  24     - Added --version and -version as aliases for -V
  25     - Improve yosys-smtbmc "solver not found" handling
  26     - Improved support of $readmem[hb] Memory Content File inclusion
  27     - Added CXXRTL backend
  28     - Use YosysHQ/abc instead of upstream berkeley-abc/abc
  29     - Added WASI platform support.
  30     - Added extmodule support to firrtl backend
  31     - Added $divfloor and $modfloor cells
  32     - Added $adffe, $dffsre, $sdff, $sdffe, $sdffce, $adlatch cells
  33     - Added "_TECHMAP_CELLNAME_" parameter for "techmap" pass
  34     - Added firrtl backend support for generic parameters in blackbox components
  35     - Added $meminit_v2 cells (with support for write mask)
  36     - Added $mem_v2, $memrd_v2, $memwr_v2, with the following features:
  37       - write priority masks, per write/write port pair
  38       - transparency and undefined collision behavior masks, per read/write port pair
  39       - read port reset and initialization
  40       - wide ports (accessing a naturally aligned power-of-two number of memory cells)
  41
  42  * New commands and options
  43     - Added "write_xaiger" backend
  44     - Added "read_xaiger"
  45     - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only)
  46     - Added "synth -abc9" (experimental)
  47     - Added "script -scriptwire"
  48     - Added "clkbufmap" pass
  49     - Added "extractinv" pass and "invertible_pin" attribute
  50     - Added "proc_clean -quiet"
  51     - Added "proc_prune" pass
  52     - Added "stat -tech cmos"
  53     - Added "opt_share" pass, run as part of "opt -full"
  54     - Added "-match-init" option to "dff2dffs" pass
  55     - Added "equiv_opt -multiclock"
  56     - Added "techmap_autopurge" support to techmap
  57     - Added "add -mod <modname[s]>"
  58     - Added "paramap" pass
  59     - Added "portlist" command
  60     - Added "check -mapped"
  61     - Added "check -allow-tbuf"
  62     - Added "autoname" pass
  63     - Added "write_verilog -extmem"
  64     - Added "opt_mem" pass
  65     - Added "scratchpad" pass
  66     - Added "fminit" pass
  67     - Added "opt_lut_ins" pass
  68     - Added "logger" pass
  69     - Added "show -nobg"
  70     - Added "exec" command
  71     - Added "design -delete"
  72     - Added "design -push-copy"
  73     - Added "qbfsat" command
  74     - Added "select -unset"
  75     - Added "dfflegalize" pass
  76     - Removed "opt_expr -clkinv" option, made it the default
  77     - Added "proc -nomux
  78     - Merged "dffsr2dff", "opt_rmdff", "dff2dffe", "dff2dffs", "peepopt.dffmux" passes into a new "opt_dff" pass
  79
  80  * SystemVerilog
  81     - Added checking of always block types (always_comb, always_latch and always_ff)
  82     - Added support for wildcard port connections (.*)
  83     - Added support for enum typedefs
  84     - Added support for structs and packed unions.
  85     - Allow constant function calls in for loops and generate if and case
  86     - Added support for static cast
  87     - Added support for logic typed parameters
  88     - Fixed generate scoping issues
  89     - Added support for real-valued parameters
  90     - Allow localparams in constant functions
  91     - Module name scope support
  92     - Support recursive functions using ternary expressions
  93     - Extended support for integer types
  94     - Support for parameters without default values
  95     - Allow globals in one file to depend on globals in another
  96     - Added support for: *=, /=, %=, <<=, >>=, <<<=, >>>=
  97     - Added support for parsing the 'bind' construct
  98     - support declaration in procedural for initialization
  99     - support declaration in generate for initialization
 100     - Support wand and wor of data types
 101
 102  * Verific support
 103     - Added "verific -L"
 104     - Add Verific SVA support for "always" properties
 105     - Add Verific support for SVA nexttime properties
 106     - Improve handling of verific primitives in "verific -import -V" mode
 107     - Import attributes for wires
 108     - Support VHDL enums
 109     - Added support for command files
 110
 111  * New back-ends
 112     - Added initial EFINIX support
 113     - Added Intel ALM: alternative synthesis for Intel FPGAs
 114     - Added initial Nexus support
 115     - Added initial MachXO2 support
 116     - Added initial QuickLogic PolarPro 3 support
 117
 118  * ECP5 support
 119     - Renamed labels/options in synth_ecp5 (e.g. dram -> map_lutram; -nodram -> -nolutram)
 120     - Added "synth_ecp5 -abc9" (experimental)
 121     - Added "synth_ecp5 -nowidelut"
 122     - "synth_ecp5" to now infer DSP blocks (-nodsp to disable, experimental)
 123
 124  * iCE40 support
 125     - Added "synth_ice40 -abc9" (experimental)
 126     - Added "synth_ice40 -device"
 127     - Renamed labels/options in synth_ice40 (e.g. dram -> map_lutram; -nodram -> -nolutram)
 128     - Added "ice40_wrapcarry" to encapsulate SB_LUT+SB_CARRY pairs for techmapping
 129     - Removed "ice40_unlut"
 130     - Added "ice40_dsp" for Lattice iCE40 DSP packing
 131     - "synth_ice40 -dsp" to infer DSP blocks
 132
 133  * Xilinx support
 134     - Added "synth_xilinx -abc9" (experimental)
 135     - Added "synth_xilinx -nocarry"
 136     - Added "synth_xilinx -nowidelut"
 137     - "synth_xilinx" to now infer wide multiplexers (-widemux <min> to enable)
 138     - Renamed labels/options in synth_xilinx (e.g. dram -> map_lutram; -nodram -> -nolutram)
 139     - Added "synth_xilinx -family xc6s" for Spartan 6 support (experimental)
 140     - Added "synth_xilinx -ise" (experimental)
 141     - Added "synth_xilinx -iopad"
 142     - "synth_xilinx" now automatically inserts clock buffers (add -noclkbuf to disable)
 143     - Added "xilinx_srl" for Xilinx shift register extraction
 144     - Removed "shregmap -tech xilinx" (superseded by "xilinx_srl")
 145     - Added "xilinx_dsp" for Xilinx DSP packing
 146     - "synth_xilinx" to now infer DSP blocks (-nodsp to disable)
 147     - Added latch support to synth_xilinx
 148     - Added support for flip-flops with synchronous reset to synth_xilinx
 149     - Added support for flip-flops with reset and enable to synth_xilinx
 150     - Added "xilinx_dffopt" pass
 151     - Added "synth_xilinx -dff"
 152
 153  * Intel support
 154     - Renamed labels in synth_intel (e.g. bram -> map_bram)
 155     - synth_intel: cyclone10 -> cyclone10lp, a10gx -> arria10gx
 156     - Added "intel_alm -abc9" (experimental)
 157
 158  * CoolRunner2 support
 159     - Separate and improve buffer cell insertion pass
 160     - Use extract_counter to optimize counters
 161
 162 Yosys 0.8 .. Yosys 0.9
 163 ----------------------
 164
 165  * Various
 166     - Many bugfixes and small improvements
 167     - Added support for SystemVerilog interfaces and modports
 168     - Added "write_edif -attrprop"
 169     - Added "opt_lut" pass
 170     - Added "gate2lut.v" techmap rule
 171     - Added "rename -src"
 172     - Added "equiv_opt" pass
 173     - Added "flowmap" LUT mapping pass
 174     - Added "rename -wire" to rename cells based on the wires they drive
 175     - Added "bugpoint" for creating minimised testcases
 176     - Added "write_edif -gndvccy"
 177     - "write_verilog" to escape Verilog keywords
 178     - Fixed sign handling of real constants
 179     - "write_verilog" to write initial statement for initial flop state
 180     - Added pmgen pattern matcher generator
 181     - Fixed opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_
 182     - Added "setundef -params" to replace undefined cell parameters
 183     - Renamed "yosys -D" to "yosys -U", added "yosys -D" to set Verilog defines
 184     - Fixed handling of defparam when default_nettype is none
 185     - Fixed "wreduce" flipflop handling
 186     - Fixed FIRRTL to Verilog process instance subfield assignment
 187     - Added "write_verilog -siminit"
 188     - Several fixes and improvements for mem2reg memories
 189     - Fixed handling of task output ports in clocked always blocks
 190     - Improved handling of and-with-1 and or-with-0 in "opt_expr"
 191     - Added "read_aiger" frontend
 192     - Added "mutate" pass
 193     - Added "hdlname" attribute
 194     - Added "rename -output"
 195     - Added "read_ilang -lib"
 196     - Improved "proc" full_case detection and handling
 197     - Added "whitebox" and "lib_whitebox" attributes
 198     - Added "read_verilog -nowb", "flatten -wb" and "wbflip"
 199     - Added Python bindings and support for Python plug-ins
 200     - Added "pmux2shiftx"
 201     - Added log_debug framework for reduced default verbosity
 202     - Improved "opt_expr" and "opt_clean" handling of (partially) undriven and/or unused wires
 203     - Added "peepopt" peephole optimisation pass using pmgen
 204     - Added approximate support for SystemVerilog "var" keyword
 205     - Added parsing of "specify" blocks into $specrule and $specify[23]
 206     - Added support for attributes on parameters and localparams
 207     - Added support for parsing attributes on port connections
 208     - Added "wreduce -keepdc"
 209     - Added support for optimising $dffe and $_DFFE_* cells in "opt_rmdff"
 210     - Added Verilog wand/wor wire type support
 211     - Added support for elaboration system tasks
 212     - Added "muxcover -mux{4,8,16}=<cost>"
 213     - Added "muxcover -dmux=<cost>"
 214     - Added "muxcover -nopartial"
 215     - Added "muxpack" pass
 216     - Added "pmux2shiftx -norange"
 217     - Added support for "~" in filename parsing
 218     - Added "read_verilog -pwires" feature to turn parameters into wires
 219     - Fixed sign extension of unsized constants with 'bx and 'bz MSB
 220     - Fixed genvar to be a signed type
 221     - Added support for attributes on case rules
 222     - Added "upto" and "offset" to JSON frontend and backend
 223     - Several liberty file parser improvements
 224     - Fixed handling of more complex BRAM patterns
 225     - Add "write_aiger -I -O -B"
 226
 227  * Formal Verification
 228     - Added $changed support to read_verilog
 229     - Added "read_verilog -noassert -noassume -assert-assumes"
 230     - Added btor ops for $mul, $div, $mod and $concat
 231     - Added yosys-smtbmc support for btor witnesses
 232     - Added "supercover" pass
 233     - Fixed $global_clock handling vs autowire
 234     - Added $dffsr support to "async2sync"
 235     - Added "fmcombine" pass
 236     - Added memory init support in "write_btor"
 237     - Added "cutpoint" pass
 238     - Changed "ne" to "neq" in btor2 output
 239     - Added support for SVA "final" keyword
 240     - Added "fmcombine -initeq -anyeq"
 241     - Added timescale and generated-by header to yosys-smtbmc vcd output
 242     - Improved BTOR2 handling of undriven wires
 243
 244  * Verific support
 245     - Enabled Verific flags vhdl_support_variable_slice and veri_elaborate_top_level_modules_having_interface_ports
 246     - Improved support for asymmetric memories
 247     - Added "verific -chparam"
 248     - Fixed "verific -extnets" for more complex situations
 249     - Added "read -verific" and "read -noverific"
 250     - Added "hierarchy -chparam"
 251
 252  * New back-ends
 253     - Added initial Anlogic support
 254     - Added initial SmartFusion2 and IGLOO2 support
 255
 256  * ECP5 support
 257     - Added "synth_ecp5 -nowidelut"
 258     - Added BRAM inference support to "synth_ecp5"
 259     - Added support for transforming Diamond IO and flipflop primitives
 260
 261  * iCE40 support
 262     - Added "ice40_unlut" pass
 263     - Added "synth_ice40 -relut"
 264     - Added "synth_ice40 -noabc"
 265     - Added "synth_ice40 -dffe_min_ce_use"
 266     - Added DSP inference support using pmgen
 267     - Added support for initialising BRAM primitives from a file
 268     - Added iCE40 Ultra RGB LED driver cells
 269
 270  * Xilinx support
 271     - Use "write_edif -pvector bra" for Xilinx EDIF files
 272     - Fixes for VPR place and route support with "synth_xilinx"
 273     - Added more cell simulation models
 274     - Added "synth_xilinx -family"
 275     - Added "stat -tech xilinx" to estimate logic cell usage
 276     - Added "synth_xilinx -nocarry"
 277     - Added "synth_xilinx -nowidelut"
 278     - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
 279     - Added support for mapping RAM32X1D
 280
 281 Yosys 0.7 .. Yosys 0.8
 282 ----------------------
 283
 284  * Various
 285     - Many bugfixes and small improvements
 286     - Strip debug symbols from installed binary
 287     - Replace -ignore_redef with -[no]overwrite in front-ends
 288     - Added write_verilog hex dump support, add -nohex option
 289     - Added "write_verilog -decimal"
 290     - Added "scc -set_attr"
 291     - Added "verilog_defines" command
 292     - Remember defines from one read_verilog to next
 293     - Added support for hierarchical defparam
 294     - Added FIRRTL back-end
 295     - Improved ABC default scripts
 296     - Added "design -reset-vlog"
 297     - Added "yosys -W regex", "yosys -w regex", and "yosys -e regex"
 298     - Added Verilog $rtoi and $itor support
 299     - Added "check -initdrv"
 300     - Added "read_blif -wideports"
 301     - Added support for SystemVerilog "++" and "--" operators
 302     - Added support for SystemVerilog unique, unique0, and priority case
 303     - Added "write_edif" options for edif "flavors"
 304     - Added support for resetall compiler directive
 305     - Added simple C beck-end (bitwise combinatorical only atm)
 306     - Added $_ANDNOT_ and $_ORNOT_ cell types
 307     - Added cell library aliases to "abc -g"
 308     - Added "setundef -anyseq"
 309     - Added "chtype" command
 310     - Added "design -import"
 311     - Added "write_table" command
 312     - Added "read_json" command
 313     - Added "sim" command
 314     - Added "extract_fa" and "extract_reduce" commands
 315     - Added "extract_counter" command
 316     - Added "opt_demorgan" command
 317     - Added support for $size and $bits SystemVerilog functions
 318     - Added "blackbox" command
 319     - Added "ltp" command
 320     - Added support for editline as replacement for readline
 321     - Added warnings for driver-driver conflicts between FFs (and other cells) and constants
 322     - Added "yosys -E" for creating Makefile dependencies files
 323     - Added "synth -noshare"
 324     - Added "memory_nordff"
 325     - Added "setundef -undef -expose -anyconst"
 326     - Added "expose -input"
 327     - Added specify/specparam parser support (simply ignore them)
 328     - Added "write_blif -inames -iattr"
 329     - Added "hierarchy -simcheck"
 330     - Added an option to statically link abc into yosys
 331     - Added protobuf back-end
 332     - Added BLIF parsing support for .conn and .cname
 333     - Added read_verilog error checking for reg/wire/logic misuse
 334     - Added "make coverage" and ENABLE_GCOV build option
 335
 336  * Changes in Yosys APIs
 337     - Added ConstEval defaultval feature
 338     - Added {get,set}_src_attribute() methods on RTLIL::AttrObject
 339     - Added SigSpec::is_fully_ones() and Const::is_fully_ones()
 340     - Added log_file_warning() and log_file_error() functions
 341
 342  * Formal Verification
 343     - Added "write_aiger"
 344     - Added "yosys-smtbmc --aig"
 345     - Added "always <positive_int>" to .smtc format
 346     - Added $cover cell type and support for cover properties
 347     - Added $fair/$live cell type and support for liveness properties
 348     - Added smtbmc support for memory vcd dumping
 349     - Added "chformal" command
 350     - Added "write_smt2 -stbv" and "write_smt2 -stdt"
 351     - Fix equiv_simple, old behavior now available with "equiv_simple -short"
 352     - Change to Yices2 as default SMT solver (it is GPL now)
 353     - Added "yosys-smtbmc --presat" (now default in SymbiYosys)
 354     - Added "yosys-smtbmc --smtc-init --smtc-top --noinit"
 355     - Added a brand new "write_btor" command for BTOR2
 356     - Added clk2fflogic memory support and other improvements
 357     - Added "async memory write" support to write_smt2
 358     - Simulate clock toggling in yosys-smtbmc VCD output
 359     - Added $allseq/$allconst cells for EA-solving
 360     - Make -nordff the default in "prep"
 361     - Added (* gclk *) attribute
 362     - Added "async2sync" pass for single-clock designs with async resets
 363
 364  * Verific support
 365     - Many improvements in Verific front-end
 366     - Added proper handling of concurent SVA properties
 367     - Map "const" and "rand const" to $anyseq/$anyconst
 368     - Added "verific -import -flatten" and "verific -import -extnets"
 369     - Added "verific -vlog-incdir -vlog-define -vlog-libdir"
 370     - Remove PSL support (because PSL has been removed in upstream Verific)
 371     - Improve integration with "hierarchy" command design elaboration
 372     - Added YOSYS_NOVERIFIC for running non-verific test cases with verific bin
 373     - Added simpilied "read" command that automatically uses verific if available
 374     - Added "verific -set-<severity> <msg_id>.."
 375     - Added "verific -work <libname>"
 376
 377  * New back-ends
 378     - Added initial Coolrunner-II support
 379     - Added initial eASIC support
 380     - Added initial ECP5 support
 381
 382  * GreenPAK Support
 383     - Added support for GP_DLATCH, GP_SPI, GP_DCMx, GP_COUNTx, etc.
 384
 385  * iCE40 Support
 386     - Add "synth_ice40 -vpr"
 387     - Add "synth_ice40 -nodffe"
 388     - Add "synth_ice40 -json"
 389     - Add Support for UltraPlus cells
 390
 391  * MAX10 and Cyclone IV Support
 392     - Added initial version of metacommand "synth_intel".
 393     - Improved write_verilog command to produce VQM netlist for Quartus Prime.
 394     - Added support for MAX10 FPGA family synthesis.
 395     - Added support for Cyclone IV family synthesis.
 396     - Added example of implementation for DE2i-150 board.
 397     - Added example of implementation for MAX10 development kit.
 398     - Added LFSR example from Asic World.
 399     - Added "dffinit -highlow" for mapping to Intel primitives
 400
 401
 402 Yosys 0.6 .. Yosys 0.7
 403 ----------------------
 404
 405  * Various
 406     - Added "yosys -D" feature
 407     - Added support for installed plugins in $(DATDIR)/plugins/
 408     - Renamed opt_const to opt_expr
 409     - Renamed opt_share to opt_merge
 410     - Added "prep -flatten" and "synth -flatten"
 411     - Added "prep -auto-top" and "synth -auto-top"
 412     - Using "mfs" and "lutpack" in ABC lut mapping
 413     - Support for abstract modules in chparam
 414     - Cleanup abstract modules at end of "hierarchy -top"
 415     - Added tristate buffer support to iopadmap
 416     - Added opt_expr support for div/mod by power-of-two
 417     - Added "select -assert-min <N> -assert-max <N>"
 418     - Added "attrmvcp" pass
 419     - Added "attrmap" command
 420     - Added "tee +INT -INT"
 421     - Added "zinit" pass
 422     - Added "setparam -type"
 423     - Added "shregmap" pass
 424     - Added "setundef -init"
 425     - Added "nlutmap -assert"
 426     - Added $sop cell type and "abc -sop -I <num> -P <num>"
 427     - Added "dc2" to default ABC scripts
 428     - Added "deminout"
 429     - Added "insbuf" command
 430     - Added "prep -nomem"
 431     - Added "opt_rmdff -keepdc"
 432     - Added "prep -nokeepdc"
 433     - Added initial version of "synth_gowin"
 434     - Added "fsm_expand -full"
 435     - Added support for fsm_encoding="user"
 436     - Many improvements in GreenPAK4 support
 437     - Added black box modules for all Xilinx 7-series lib cells
 438     - Added synth_ice40 support for latches via logic loops
 439     - Fixed ice40_opt lut unmapping, added "ice40_opt -unlut"
 440
 441  * Build System
 442     - Added ABCEXTERNAL and ABCURL make variables
 443     - Added BINDIR, LIBDIR, and DATDIR make variables
 444     - Added PKG_CONFIG make variable
 445     - Added SEED make variable (for "make test")
 446     - Added YOSYS_VER_STR make variable
 447     - Updated min GCC requirement to GCC 4.8
 448     - Updated required Bison version to Bison 3.x
 449
 450  * Internal APIs
 451     - Added ast.h to exported headers
 452     - Added ScriptPass helper class for script-like passes
 453     - Added CellEdgesDatabase API
 454
 455  * Front-ends and Back-ends
 456     - Added filename glob support to all front-ends
 457     - Added avail (black-box) module params to ilang format
 458     - Added $display %m support
 459     - Added support for $stop Verilog system task
 460     - Added support for SystemVerilog packages
 461     - Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b}
 462     - Added support for "active high" and "active low" latches in read_blif and write_blif
 463     - Use init value "2" for all uninitialized FFs in BLIF back-end
 464     - Added "read_blif -sop"
 465     - Added "write_blif -noalias"
 466     - Added various write_blif options for VTR support
 467     - write_json: also write module attributes.
 468     - Added "write_verilog -nodec -nostr -defparam"
 469     - Added "read_verilog -norestrict -assume-asserts"
 470     - Added support for bus interfaces to "read_liberty -lib"
 471     - Added liberty parser support for types within cell decls
 472     - Added "write_verilog -renameprefix -v"
 473     - Added "write_edif -nogndvcc"
 474
 475  * Formal Verification
 476     - Support for hierarchical designs in smt2 back-end
 477     - Yosys-smtbmc: Support for hierarchical VCD dumping
 478     - Added $initstate cell type and vlog function
 479     - Added $anyconst and $anyseq cell types and vlog functions
 480     - Added printing of code loc of failed asserts to yosys-smtbmc
 481     - Added memory_memx pass, "memory -memx", and "prep -memx"
 482     - Added "proc_mux -ifx"
 483     - Added "yosys-smtbmc -g"
 484     - Deprecated "write_smt2 -regs" (by default on now)
 485     - Made "write_smt2 -bv -mem" default, added "write_smt2 -nobv -nomem"
 486     - Added support for memories to smtio.py
 487     - Added "yosys-smtbmc --dump-vlogtb"
 488     - Added "yosys-smtbmc --smtc --dump-smtc"
 489     - Added "yosys-smtbmc --dump-all"
 490     - Added assertpmux command
 491     - Added "yosys-smtbmc --unroll"
 492     - Added $past, $stable, $rose, $fell SVA functions
 493     - Added "yosys-smtbmc --noinfo and --dummy"
 494     - Added "yosys-smtbmc --noincr"
 495     - Added "yosys-smtbmc --cex <filename>"
 496     - Added $ff and $_FF_ cell types
 497     - Added $global_clock verilog syntax support for creating $ff cells
 498     - Added clk2fflogic
 499
 500
 501 Yosys 0.5 .. Yosys 0.6
 502 ----------------------
 503
 504  * Various
 505      - Added Contributor Covenant Code of Conduct
 506      - Various improvements in dict<> and pool<>
 507      - Added hashlib::mfp and refactored SigMap
 508      - Improved support for reals as module parameters
 509      - Various improvements in SMT2 back-end
 510      - Added "keep_hierarchy" attribute
 511      - Verilog front-end: define `BLACKBOX in -lib mode
 512      - Added API for converting internal cells to AIGs
 513      - Added ENABLE_LIBYOSYS Makefile option
 514      - Removed "techmap -share_map" (use "-map +/filename" instead)
 515      - Switched all Python scripts to Python 3
 516      - Added support for $display()/$write() and $finish() to Verilog front-end
 517      - Added "yosys-smtbmc" formal verification flow
 518      - Added options for clang sanitizers to Makefile
 519
 520  * New commands and options
 521      - Added "scc -expect <N> -nofeedback"
 522      - Added "proc_dlatch"
 523      - Added "check"
 524      - Added "select %xe %cie %coe %M %C %R"
 525      - Added "sat -dump_json" (WaveJSON format)
 526      - Added "sat -tempinduct-baseonly -tempinduct-inductonly"
 527      - Added "sat -stepsize" and "sat -tempinduct-step"
 528      - Added "sat -show-regs -show-public -show-all"
 529      - Added "write_json" (Native Yosys JSON format)
 530      - Added "write_blif -attr"
 531      - Added "dffinit"
 532      - Added "chparam"
 533      - Added "muxcover"
 534      - Added "pmuxtree"
 535      - Added memory_bram "make_outreg" feature
 536      - Added "splice -wires"
 537      - Added "dff2dffe -direct-match"
 538      - Added simplemap $lut support
 539      - Added "read_blif"
 540      - Added "opt_share -share_all"
 541      - Added "aigmap"
 542      - Added "write_smt2 -mem -regs -wires"
 543      - Added "memory -nordff"
 544      - Added "write_smv"
 545      - Added "synth -nordff -noalumacc"
 546      - Added "rename -top new_name"
 547      - Added "opt_const -clkinv"
 548      - Added "synth -nofsm"
 549      - Added "miter -assert"
 550      - Added "read_verilog -noautowire"
 551      - Added "read_verilog -nodpi"
 552      - Added "tribuf"
 553      - Added "lut2mux"
 554      - Added "nlutmap"
 555      - Added "qwp"
 556      - Added "test_cell -noeval"
 557      - Added "edgetypes"
 558      - Added "equiv_struct"
 559      - Added "equiv_purge"
 560      - Added "equiv_mark"
 561      - Added "equiv_add -try -cell"
 562      - Added "singleton"
 563      - Added "abc -g -luts"
 564      - Added "torder"
 565      - Added "write_blif -cname"
 566      - Added "submod -copy"
 567      - Added "dffsr2dff"
 568      - Added "stat -liberty"
 569
 570  * Synthesis metacommands
 571      - Various improvements in synth_xilinx
 572      - Added synth_ice40 and synth_greenpak4
 573      - Added "prep" metacommand for "synthesis lite"
 574
 575  * Cell library changes
 576      - Added cell types to "help" system
 577      - Added $meminit cell type
 578      - Added $assume cell type
 579      - Added $_MUX4_, $_MUX8_, and $_MUX16_ cells
 580      - Added $tribuf and $_TBUF_ cell types
 581      - Added read-enable to memory model
 582
 583  * YosysJS
 584      - Various improvements in emscripten build
 585      - Added alternative webworker-based JS API
 586      - Added a few example applications
 587
 588
 589 Yosys 0.4 .. Yosys 0.5
 590 ----------------------
 591
 592  * API changes
 593      - Added log_warning()
 594      - Added eval_select_args() and eval_select_op()
 595      - Added cell->known(), cell->input(portname), cell->output(portname)
 596      - Skip blackbox modules in design->selected_modules()
 597      - Replaced std::map<> and std::set<> with dict<> and pool<>
 598      - New SigSpec::extend() is what used to be SigSpec::extend_u0()
 599      - Added YS_OVERRIDE, YS_FINAL, YS_ATTRIBUTE, YS_NORETURN
 600
 601  * Cell library changes
 602      - Added flip-flops with enable ($dffe etc.)
 603      - Added $equiv cells for equivalence checking framework
 604
 605  * Various
 606      - Updated ABC to hg rev 61ad5f908c03
 607      - Added clock domain partitioning to ABC pass
 608      - Improved plugin building (see "yosys-config --build")
 609      - Added ENABLE_NDEBUG Makefile flag for high-performance builds
 610      - Added "yosys -d", "yosys -L" and other driver improvements
 611      - Added support for multi-bit (array) cell ports to "write_edif"
 612      - Now printing most output to stdout, not stderr
 613      - Added "onehot" attribute (set by "fsm_map")
 614      - Various performance improvements
 615      - Vastly improved Xilinx flow
 616      - Added "make unsintall"
 617
 618  * Equivalence checking
 619      - Added equivalence checking commands:
 620          equiv_make equiv_simple equiv_status
 621          equiv_induct equiv_miter
 622          equiv_add equiv_remove
 623
 624  * Block RAM support:
 625      - Added "memory_bram" command
 626      - Added BRAM support to Xilinx flow
 627
 628  * Other New Commands and Options
 629      - Added "dff2dffe"
 630      - Added "fsm -encfile"
 631      - Added "dfflibmap -prepare"
 632      - Added "write_blid -unbuf -undef -blackbox"
 633      - Added "write_smt2" for writing SMT-LIBv2 files
 634      - Added "test_cell -w -muxdiv"
 635      - Added "select -read"
 636
 637
 638 Yosys 0.3.0 .. Yosys 0.4
 639 ------------------------
 640
 641  * Platform Support
 642      - Added support for mxe-based cross-builds for win32
 643      - Added sourcecode-export as VisualStudio project
 644      - Added experimental EMCC (JavaScript) support
 645
 646  * Verilog Frontend
 647      - Added -sv option for SystemVerilog (and automatic *.sv file support)
 648      - Added support for real-valued constants and constant expressions
 649      - Added support for non-standard "via_celltype" attribute on task/func
 650      - Added support for non-standard "module mod_name(...);" syntax
 651      - Added support for non-standard """ macro bodies
 652      - Added support for array with more than one dimension
 653      - Added support for $readmemh and $readmemb
 654      - Added support for DPI functions
 655
 656  * Changes in internal cell library
 657      - Added $shift and $shiftx cell types
 658      - Added $alu, $lcu, $fa and $macc cell types
 659      - Removed $bu0 and $safe_pmux cell types
 660      - $mem/$memwr WR_EN input is now a per-data-bit enable signal
 661      - Added $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
 662      - Renamed ports of $lut cells (from I->O to A->Y)
 663      - Renamed $_INV_ to $_NOT_
 664
 665  * Changes for simple synthesis flows
 666      - There is now a "synth" command with a recommended default script
 667      - Many improvements in synthesis of arithmetic functions to gates
 668          - Multipliers and adders with many operands are using carry-save adder trees
 669          - Remaining adders are now implemented using Brent-Kung carry look-ahead adders
 670      - Various new high-level optimizations on RTL netlist
 671      - Various improvements in FSM optimization
 672      - Updated ABC to hg 5b5af75f1dda (from 2014-11-07)
 673
 674  * Changes in internal APIs and RTLIL
 675      - Added log_id() and log_cell() helper functions
 676      - Added function-like cell creation helpers
 677      - Added GetSize() function (like .size() but with int)
 678      - Major refactoring of RTLIL::Module and related classes
 679      - Major refactoring of RTLIL::SigSpec and related classes
 680      - Now RTLIL::IdString is essentially an int
 681      - Added macros for code coverage counters
 682      - Added some Makefile magic for pretty make logs
 683      - Added "kernel/yosys.h" with all the core definitions
 684      - Changed a lot of code from FILE* to c++ streams
 685      - Added RTLIL::Monitor API and "trace" command
 686      - Added "Yosys" C++ namespace
 687
 688  * Changes relevant to SAT solving
 689      - Added ezSAT::keep_cnf() and ezSAT::non_incremental()
 690      - Added native ezSAT support for vector shift ops
 691      - Updated MiniSAT to git 37dc6c67e2 (from 2013-09-25)
 692
 693  * New commands (or large improvements to commands)
 694      - Added "synth" command with default script
 695      - Added "share" (finally some real resource sharing)
 696      - Added "memory_share" (reduce number of ports on memories)
 697      - Added "wreduce" and "alumacc" commands
 698      - Added "opt -keepdc -fine -full -fast"
 699      - Added some "test_*" commands
 700
 701  * Various other changes
 702      - Added %D and %c select operators
 703      - Added support for labels in yosys scripts
 704      - Added support for here-documents in yosys scripts
 705      - Support "+/" prefix for files from proc_share_dir
 706      - Added "autoidx" statement to ilang language
 707      - Switched from "yosys-svgviewer" to "xdot"
 708      - Renamed "stdcells.v" to "techmap.v"
 709      - Various bug fixes and small improvements
 710      - Improved welcome and bye messages
 711
 712
 713 Yosys 0.2.0 .. Yosys 0.3.0
 714 --------------------------
 715
 716  * Driver program and overall behavior:
 717      - Added "design -push" and "design -pop"
 718      - Added "tee" command for redirecting log output
 719
 720  * Changes in the internal cell library:
 721      - Added $dlatchsr and $_DLATCHSR_???_ cell types
 722
 723  * Improvements in Verilog frontend:
 724      - Improved support for const functions (case, always, repeat)
 725      - The generate..endgenerate keywords are now optional
 726      - Added support for arrays of module instances
 727      - Added support for "`default_nettype" directive
 728      - Added support for "`line" directive
 729
 730  * Other front- and back-ends:
 731      - Various changes to "write_blif" options
 732      - Various improvements in EDIF backend
 733      - Added "vhdl2verilog" pseudo-front-end
 734      - Added "verific" pseudo-front-end
 735
 736  * Improvements in technology mapping:
 737      - Added support for recursive techmap
 738      - Added CONSTMSK and CONSTVAL features to techmap
 739      - Added _TECHMAP_CONNMAP_*_ feature to techmap
 740      - Added _TECHMAP_REPLACE_ feature to techmap
 741      - Added "connwrappers" command for wrap-extract-unwrap method
 742      - Added "extract -map %<design_name>" feature
 743      - Added "extract -ignore_param ..." and "extract -ignore_parameters"
 744      - Added "techmap -max_iter" option
 745
 746  * Improvements to "eval" and "sat" framework:
 747      - Now include a copy of Minisat (with build fixes applied)
 748      - Switched to Minisat::SimpSolver as SAT back-end
 749      - Added "sat -dump_vcd" feature
 750      - Added "sat -dump_cnf" feature
 751      - Added "sat -initsteps <N>" feature
 752      - Added "freduce -stop <N>" feature
 753      - Added "freduce -dump <prefix>" feature
 754
 755  * Integration with ABC:
 756      - Updated ABC rev to 7600ffb9340c
 757
 758  * Improvements in the internal APIs:
 759      - Added RTLIL::Module::add... helper methods
 760      - Various build fixes for OSX (Darwin) and OpenBSD
 761
 762
 763 Yosys 0.1.0 .. Yosys 0.2.0
 764 --------------------------
 765
 766  * Changes to the driver program:
 767      - Added "yosys -h" and "yosys -H"
 768      - Added support for backslash line continuation in scripts
 769      - Added support for #-comments in same line as command
 770      - Added "echo" and "log" commands
 771
 772  * Improvements in Verilog frontend:
 773      - Added support for local registers in named blocks
 774      - Added support for "case" in "generate" blocks
 775      - Added support for $clog2 system function
 776      - Added support for basic SystemVerilog assert statements
 777      - Added preprocessor support for macro arguments
 778      - Added preprocessor support for `elsif statement
 779      - Added "verilog_defaults" command
 780      - Added read_verilog -icells option
 781      - Added support for constant sizes from parameters
 782      - Added "read_verilog -setattr"
 783      - Added support for function returning 'integer'
 784      - Added limited support for function calls in parameter values
 785      - Added "read_verilog -defer" to suppress evaluation of modules with default parameters
 786
 787  * Other front- and back-ends:
 788      - Added BTOR backend
 789      - Added Liberty frontend
 790
 791  * Improvements in technology mapping:
 792      - The "dfflibmap" command now strongly prefers solutions with
 793            no inverters in clock paths
 794      - The "dfflibmap" command now prefers cells with smaller area
 795      - Added support for multiple -map options to techmap
 796      - Added "dfflibmap" support for //-comments in liberty files
 797      - Added "memory_unpack" command to revert "memory_collect"
 798      - Added standard techmap rule "techmap -share_map pmux2mux.v"
 799      - Added "iopadmap -bits"
 800      - Added "setundef" command
 801      - Added "hilomap" command
 802
 803  * Changes in the internal cell library:
 804      - Major rewrite of simlib.v for better compatibility with other tools
 805      - Added PRIORITY parameter to $memwr cells
 806      - Added TRANSPARENT parameter to $memrd cells
 807      - Added RD_TRANSPARENT parameter to $mem cells
 808      - Added $bu0 cell (always 0-extend, even undef MSB)
 809      - Added $assert cell type
 810      - Added $slice and $concat cell types
 811
 812  * Integration with ABC:
 813      - Updated ABC to hg rev 2058c8ccea68
 814      - Tighter integration of ABC build with Yosys build. The make
 815            targets 'make abc' and 'make install-abc' are now obsolete.
 816      - Added support for passing FFs from one clock domain through ABC
 817      - Now always use BLIF as exchange format with ABC
 818      - Added support for "abc -script +<command_sequence>"
 819      - Improved standard ABC recipe
 820      - Added support for "keep" attribute to abc command
 821      - Added "abc -dff / -clk / -keepff" options
 822
 823  * Improvements to "eval" and "sat" framework:
 824      - Added support for "0" and "~0" in right-hand side -set expressions
 825      - Added "eval -set-undef" and "eval -table"
 826      - Added "sat -set-init" and "sat -set-init-*" for sequential problems
 827      - Added undef support to SAT solver, incl. various new "sat" options
 828      - Added correct support for === and !== for "eval" and "sat"
 829      - Added "sat -tempinduct" (default -seq is now non-induction sequential)
 830      - Added "sat -prove-asserts"
 831      - Complete rewrite of the 'freduce' command
 832      - Added "miter" command
 833      - Added "sat -show-inputs" and "sat -show-outputs"
 834      - Added "sat -ignore_unknown_cells" (now produce an error by default)
 835      - Added "sat -falsify"
 836      - Now "sat -verify" and "sat -falsify" can also be used without "-prove"
 837      - Added "expose" command
 838      - Added support for @<sel_name> to sat and eval signal expressions
 839
 840  * Changes in the 'make test' framework and auxiliary test tools:
 841      - Added autotest.sh -p and -f options
 842      - Replaced autotest.sh ISIM support with XSIM support
 843      - Added test cases for SAT framework
 844
 845  * Added "abbreviated IDs":
 846      - Now $<something>$foo can be abbreviated as $foo.
 847      - Usually this last part is a unique id (from RTLIL::autoidx)
 848      - This abbreviated IDs are now also used in "show" output
 849
 850  * Other changes to selection framework:
 851      - Now */ is optional in */<mode>:<arg> expressions
 852      - Added "select -assert-none" and "select -assert-any"
 853      - Added support for matching modules by attribute (A:<expr>)
 854      - Added "select -none"
 855      - Added support for r:<expr> pattern for matching cell parameters
 856      - Added support for !=, <, <=, >=, > for attribute and parameter matching
 857      - Added support for %s for selecting sub-modules
 858      - Added support for %m for expanding selections to whole modules
 859      - Added support for i:*, o:* and x:* pattern for selecting module ports
 860      - Added support for s:<expr> pattern for matching wire width
 861      - Added support for %a operation to select wire aliases
 862
 863  * Various other changes to commands and options:
 864      - The "ls" command now supports wildcards
 865      - Added "show -pause" and "show -format dot"
 866      - Added "show -color" support for cells
 867      - Added "show -label" and "show -notitle"
 868      - Added "dump -m" and "dump -n"
 869      - Added "history" command
 870      - Added "rename -hide"
 871      - Added "connect" command
 872      - Added "splitnets -driver"
 873      - Added "opt_const -mux_undef"
 874      - Added "opt_const -mux_bool"
 875      - Added "opt_const -undriven"
 876      - Added "opt -mux_undef -mux_bool -undriven -purge"
 877      - Added "hierarchy -libdir"
 878      - Added "hierarchy -purge_lib" (by default now do not remove lib cells)
 879      - Added "delete" command
 880      - Added "dump -append"
 881      - Added "setattr" and "setparam" commands
 882      - Added "design -stash/-copy-from/-copy-to"
 883      - Added "copy" command
 884      - Added "splice" command
 885