CHANGELOG

   1
   2 List of major changes and improvements between releases
   3 =======================================================
   4
   5 Yosys 0.14 .. Yosys 0.14-dev
   6 --------------------------
   7
   8 Yosys 0.13 .. Yosys 0.14
   9 --------------------------
  10
  11  * Various
  12     - Added $bmux and $demux cells and related optimization patterns.
  13
  14  * New commands and options
  15     - Added "bmuxmap" and "dmuxmap" passes
  16     - Added "-fst" option to "sim" pass for writing FST files
  17     - Added "-r", "-scope", "-start", "-stop", "-at", "-sim", "-sim-gate",
  18       "-sim-gold" options to "sim" pass for co-simulation
  19
  20  * Anlogic support
  21     - Added support for BRAMs
  22
  23 Yosys 0.12 .. Yosys 0.13
  24 --------------------------
  25
  26  * Various
  27     - Use "read" command to parse HDL files from Yosys command-line
  28     - Added "yosys -r <topmodule>" command line option
  29     - write_verilog: dump zero width sigspecs correctly
  30
  31  * SystemVerilog
  32     - Fixed regression preventing the use array querying functions in case
  33       expressions and case item expressions
  34     - Fixed static size casts inadvertently limiting the result width of binary
  35       operations
  36     - Fixed static size casts ignoring expression signedness
  37     - Fixed static size casts not extending unbased unsized literals
  38     - Added automatic `nosync` inference for local variables in `always_comb`
  39       procedures which are always assigned before they are used to avoid errant
  40       latch inference
  41
  42  * New commands and options
  43     - Added "clean_zerowidth" pass
  44
  45  * Verific support
  46     - Add YOSYS to the implicitly defined verilog macros in verific
  47
  48 Yosys 0.11 .. Yosys 0.12
  49 --------------------------
  50
  51  * Various
  52     - Added iopadmap native support for negative-polarity output enable
  53     - ABC update
  54
  55  * SystemVerilog
  56     - Support parameters using struct as a wiretype
  57
  58  * New commands and options
  59     - Added "-genlib" option to "abc" pass
  60     - Added "sta" very crude static timing analysis pass
  61
  62  * Verific support
  63     - Fixed memory block size in import
  64
  65  * New back-ends
  66     - Added support for GateMate FPGA from Cologne Chip AG
  67
  68  * Intel ALM support
  69     - Added preliminary Arria V support
  70
  71
  72 Yosys 0.10 .. Yosys 0.11
  73 --------------------------
  74
  75  * Various
  76     - Added $aldff and $aldffe (flip-flops with async load) cells
  77
  78  * SystemVerilog
  79     - Fixed an issue which prevented writing directly to a memory word via a
  80       connection to an output port
  81     - Fixed an issue which prevented unbased unsized literals (e.g., `'1`) from
  82       filling the width of a cell input
  83     - Fixed an issue where connecting a slice covering the entirety of a signed
  84       signal to a cell input would cause a failed assertion
  85
  86  * Verific support
  87     - Importer support for {PRIM,WIDE_OPER}_DFF
  88     - Importer support for PRIM_BUFIF1
  89     - Option to use Verific without VHDL support
  90     - Importer support for {PRIM,WIDE_OPER}_DLATCH{,RS}
  91     - Added -cfg option for getting/setting Verific runtime flags
  92
  93 Yosys 0.9 .. Yosys 0.10
  94 --------------------------
  95
  96  * Various
  97     - Added automatic gzip decompression for frontends
  98     - Added $_NMUX_ cell type
  99     - Added automatic gzip compression (based on filename extension) for backends
 100     - Improve attribute and parameter encoding in JSON to avoid ambiguities between
 101       bit vectors and strings containing [01xz]*
 102     - Improvements in pmgen: subpattern and recursive matches
 103     - Support explicit FIRRTL properties
 104     - Improvements in pmgen: slices, choices, define, generate
 105     - Added "_TECHMAP_WIREINIT_*_" parameter and "_TECHMAP_REMOVEINIT_*_" wire for "techmap" pass
 106     - Added +/mul2dsp.v for decomposing wide multipliers to custom-sized ones
 107     - Added new frontend: rpc
 108     - Added --version and -version as aliases for -V
 109     - Improve yosys-smtbmc "solver not found" handling
 110     - Improved support of $readmem[hb] Memory Content File inclusion
 111     - Added CXXRTL backend
 112     - Use YosysHQ/abc instead of upstream berkeley-abc/abc
 113     - Added WASI platform support.
 114     - Added extmodule support to firrtl backend
 115     - Added $divfloor and $modfloor cells
 116     - Added $adffe, $dffsre, $sdff, $sdffe, $sdffce, $adlatch cells
 117     - Added "_TECHMAP_CELLNAME_" parameter for "techmap" pass
 118     - Added firrtl backend support for generic parameters in blackbox components
 119     - Added $meminit_v2 cells (with support for write mask)
 120     - Added $mem_v2, $memrd_v2, $memwr_v2, with the following features:
 121       - write priority masks, per write/write port pair
 122       - transparency and undefined collision behavior masks, per read/write port pair
 123       - read port reset and initialization
 124       - wide ports (accessing a naturally aligned power-of-two number of memory cells)
 125
 126  * New commands and options
 127     - Added "write_xaiger" backend
 128     - Added "read_xaiger"
 129     - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only)
 130     - Added "synth -abc9" (experimental)
 131     - Added "script -scriptwire"
 132     - Added "clkbufmap" pass
 133     - Added "extractinv" pass and "invertible_pin" attribute
 134     - Added "proc_clean -quiet"
 135     - Added "proc_prune" pass
 136     - Added "stat -tech cmos"
 137     - Added "opt_share" pass, run as part of "opt -full"
 138     - Added "-match-init" option to "dff2dffs" pass
 139     - Added "equiv_opt -multiclock"
 140     - Added "techmap_autopurge" support to techmap
 141     - Added "add -mod <modname[s]>"
 142     - Added "paramap" pass
 143     - Added "portlist" command
 144     - Added "check -mapped"
 145     - Added "check -allow-tbuf"
 146     - Added "autoname" pass
 147     - Added "write_verilog -extmem"
 148     - Added "opt_mem" pass
 149     - Added "scratchpad" pass
 150     - Added "fminit" pass
 151     - Added "opt_lut_ins" pass
 152     - Added "logger" pass
 153     - Added "show -nobg"
 154     - Added "exec" command
 155     - Added "design -delete"
 156     - Added "design -push-copy"
 157     - Added "qbfsat" command
 158     - Added "select -unset"
 159     - Added "dfflegalize" pass
 160     - Removed "opt_expr -clkinv" option, made it the default
 161     - Added "proc -nomux
 162     - Merged "dffsr2dff", "opt_rmdff", "dff2dffe", "dff2dffs", "peepopt.dffmux" passes into a new "opt_dff" pass
 163
 164  * SystemVerilog
 165     - Added checking of always block types (always_comb, always_latch and always_ff)
 166     - Added support for wildcard port connections (.*)
 167     - Added support for enum typedefs
 168     - Added support for structs and packed unions.
 169     - Allow constant function calls in for loops and generate if and case
 170     - Added support for static cast
 171     - Added support for logic typed parameters
 172     - Fixed generate scoping issues
 173     - Added support for real-valued parameters
 174     - Allow localparams in constant functions
 175     - Module name scope support
 176     - Support recursive functions using ternary expressions
 177     - Extended support for integer types
 178     - Support for parameters without default values
 179     - Allow globals in one file to depend on globals in another
 180     - Added support for: *=, /=, %=, <<=, >>=, <<<=, >>>=
 181     - Added support for parsing the 'bind' construct
 182     - support declaration in procedural for initialization
 183     - support declaration in generate for initialization
 184     - Support wand and wor of data types
 185
 186  * Verific support
 187     - Added "verific -L"
 188     - Add Verific SVA support for "always" properties
 189     - Add Verific support for SVA nexttime properties
 190     - Improve handling of verific primitives in "verific -import -V" mode
 191     - Import attributes for wires
 192     - Support VHDL enums
 193     - Added support for command files
 194
 195  * New back-ends
 196     - Added initial EFINIX support
 197     - Added Intel ALM: alternative synthesis for Intel FPGAs
 198     - Added initial Nexus support
 199     - Added initial MachXO2 support
 200     - Added initial QuickLogic PolarPro 3 support
 201
 202  * ECP5 support
 203     - Renamed labels/options in synth_ecp5 (e.g. dram -> map_lutram; -nodram -> -nolutram)
 204     - Added "synth_ecp5 -abc9" (experimental)
 205     - Added "synth_ecp5 -nowidelut"
 206     - "synth_ecp5" to now infer DSP blocks (-nodsp to disable, experimental)
 207
 208  * iCE40 support
 209     - Added "synth_ice40 -abc9" (experimental)
 210     - Added "synth_ice40 -device"
 211     - Renamed labels/options in synth_ice40 (e.g. dram -> map_lutram; -nodram -> -nolutram)
 212     - Added "ice40_wrapcarry" to encapsulate SB_LUT+SB_CARRY pairs for techmapping
 213     - Removed "ice40_unlut"
 214     - Added "ice40_dsp" for Lattice iCE40 DSP packing
 215     - "synth_ice40 -dsp" to infer DSP blocks
 216
 217  * Xilinx support
 218     - Added "synth_xilinx -abc9" (experimental)
 219     - Added "synth_xilinx -nocarry"
 220     - Added "synth_xilinx -nowidelut"
 221     - "synth_xilinx" to now infer wide multiplexers (-widemux <min> to enable)
 222     - Renamed labels/options in synth_xilinx (e.g. dram -> map_lutram; -nodram -> -nolutram)
 223     - Added "synth_xilinx -family xc6s" for Spartan 6 support (experimental)
 224     - Added "synth_xilinx -ise" (experimental)
 225     - Added "synth_xilinx -iopad"
 226     - "synth_xilinx" now automatically inserts clock buffers (add -noclkbuf to disable)
 227     - Added "xilinx_srl" for Xilinx shift register extraction
 228     - Removed "shregmap -tech xilinx" (superseded by "xilinx_srl")
 229     - Added "xilinx_dsp" for Xilinx DSP packing
 230     - "synth_xilinx" to now infer DSP blocks (-nodsp to disable)
 231     - Added latch support to synth_xilinx
 232     - Added support for flip-flops with synchronous reset to synth_xilinx
 233     - Added support for flip-flops with reset and enable to synth_xilinx
 234     - Added "xilinx_dffopt" pass
 235     - Added "synth_xilinx -dff"
 236
 237  * Intel support
 238     - Renamed labels in synth_intel (e.g. bram -> map_bram)
 239     - synth_intel: cyclone10 -> cyclone10lp, a10gx -> arria10gx
 240     - Added "intel_alm -abc9" (experimental)
 241
 242  * CoolRunner2 support
 243     - Separate and improve buffer cell insertion pass
 244     - Use extract_counter to optimize counters
 245
 246 Yosys 0.8 .. Yosys 0.9
 247 ----------------------
 248
 249  * Various
 250     - Many bugfixes and small improvements
 251     - Added support for SystemVerilog interfaces and modports
 252     - Added "write_edif -attrprop"
 253     - Added "opt_lut" pass
 254     - Added "gate2lut.v" techmap rule
 255     - Added "rename -src"
 256     - Added "equiv_opt" pass
 257     - Added "flowmap" LUT mapping pass
 258     - Added "rename -wire" to rename cells based on the wires they drive
 259     - Added "bugpoint" for creating minimised testcases
 260     - Added "write_edif -gndvccy"
 261     - "write_verilog" to escape Verilog keywords
 262     - Fixed sign handling of real constants
 263     - "write_verilog" to write initial statement for initial flop state
 264     - Added pmgen pattern matcher generator
 265     - Fixed opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_
 266     - Added "setundef -params" to replace undefined cell parameters
 267     - Renamed "yosys -D" to "yosys -U", added "yosys -D" to set Verilog defines
 268     - Fixed handling of defparam when default_nettype is none
 269     - Fixed "wreduce" flipflop handling
 270     - Fixed FIRRTL to Verilog process instance subfield assignment
 271     - Added "write_verilog -siminit"
 272     - Several fixes and improvements for mem2reg memories
 273     - Fixed handling of task output ports in clocked always blocks
 274     - Improved handling of and-with-1 and or-with-0 in "opt_expr"
 275     - Added "read_aiger" frontend
 276     - Added "mutate" pass
 277     - Added "hdlname" attribute
 278     - Added "rename -output"
 279     - Added "read_ilang -lib"
 280     - Improved "proc" full_case detection and handling
 281     - Added "whitebox" and "lib_whitebox" attributes
 282     - Added "read_verilog -nowb", "flatten -wb" and "wbflip"
 283     - Added Python bindings and support for Python plug-ins
 284     - Added "pmux2shiftx"
 285     - Added log_debug framework for reduced default verbosity
 286     - Improved "opt_expr" and "opt_clean" handling of (partially) undriven and/or unused wires
 287     - Added "peepopt" peephole optimisation pass using pmgen
 288     - Added approximate support for SystemVerilog "var" keyword
 289     - Added parsing of "specify" blocks into $specrule and $specify[23]
 290     - Added support for attributes on parameters and localparams
 291     - Added support for parsing attributes on port connections
 292     - Added "wreduce -keepdc"
 293     - Added support for optimising $dffe and $_DFFE_* cells in "opt_rmdff"
 294     - Added Verilog wand/wor wire type support
 295     - Added support for elaboration system tasks
 296     - Added "muxcover -mux{4,8,16}=<cost>"
 297     - Added "muxcover -dmux=<cost>"
 298     - Added "muxcover -nopartial"
 299     - Added "muxpack" pass
 300     - Added "pmux2shiftx -norange"
 301     - Added support for "~" in filename parsing
 302     - Added "read_verilog -pwires" feature to turn parameters into wires
 303     - Fixed sign extension of unsized constants with 'bx and 'bz MSB
 304     - Fixed genvar to be a signed type
 305     - Added support for attributes on case rules
 306     - Added "upto" and "offset" to JSON frontend and backend
 307     - Several liberty file parser improvements
 308     - Fixed handling of more complex BRAM patterns
 309     - Add "write_aiger -I -O -B"
 310
 311  * Formal Verification
 312     - Added $changed support to read_verilog
 313     - Added "read_verilog -noassert -noassume -assert-assumes"
 314     - Added btor ops for $mul, $div, $mod and $concat
 315     - Added yosys-smtbmc support for btor witnesses
 316     - Added "supercover" pass
 317     - Fixed $global_clock handling vs autowire
 318     - Added $dffsr support to "async2sync"
 319     - Added "fmcombine" pass
 320     - Added memory init support in "write_btor"
 321     - Added "cutpoint" pass
 322     - Changed "ne" to "neq" in btor2 output
 323     - Added support for SVA "final" keyword
 324     - Added "fmcombine -initeq -anyeq"
 325     - Added timescale and generated-by header to yosys-smtbmc vcd output
 326     - Improved BTOR2 handling of undriven wires
 327
 328  * Verific support
 329     - Enabled Verific flags vhdl_support_variable_slice and veri_elaborate_top_level_modules_having_interface_ports
 330     - Improved support for asymmetric memories
 331     - Added "verific -chparam"
 332     - Fixed "verific -extnets" for more complex situations
 333     - Added "read -verific" and "read -noverific"
 334     - Added "hierarchy -chparam"
 335
 336  * New back-ends
 337     - Added initial Anlogic support
 338     - Added initial SmartFusion2 and IGLOO2 support
 339
 340  * ECP5 support
 341     - Added "synth_ecp5 -nowidelut"
 342     - Added BRAM inference support to "synth_ecp5"
 343     - Added support for transforming Diamond IO and flipflop primitives
 344
 345  * iCE40 support
 346     - Added "ice40_unlut" pass
 347     - Added "synth_ice40 -relut"
 348     - Added "synth_ice40 -noabc"
 349     - Added "synth_ice40 -dffe_min_ce_use"
 350     - Added DSP inference support using pmgen
 351     - Added support for initialising BRAM primitives from a file
 352     - Added iCE40 Ultra RGB LED driver cells
 353
 354  * Xilinx support
 355     - Use "write_edif -pvector bra" for Xilinx EDIF files
 356     - Fixes for VPR place and route support with "synth_xilinx"
 357     - Added more cell simulation models
 358     - Added "synth_xilinx -family"
 359     - Added "stat -tech xilinx" to estimate logic cell usage
 360     - Added "synth_xilinx -nocarry"
 361     - Added "synth_xilinx -nowidelut"
 362     - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
 363     - Added support for mapping RAM32X1D
 364
 365 Yosys 0.7 .. Yosys 0.8
 366 ----------------------
 367
 368  * Various
 369     - Many bugfixes and small improvements
 370     - Strip debug symbols from installed binary
 371     - Replace -ignore_redef with -[no]overwrite in front-ends
 372     - Added write_verilog hex dump support, add -nohex option
 373     - Added "write_verilog -decimal"
 374     - Added "scc -set_attr"
 375     - Added "verilog_defines" command
 376     - Remember defines from one read_verilog to next
 377     - Added support for hierarchical defparam
 378     - Added FIRRTL back-end
 379     - Improved ABC default scripts
 380     - Added "design -reset-vlog"
 381     - Added "yosys -W regex", "yosys -w regex", and "yosys -e regex"
 382     - Added Verilog $rtoi and $itor support
 383     - Added "check -initdrv"
 384     - Added "read_blif -wideports"
 385     - Added support for SystemVerilog "++" and "--" operators
 386     - Added support for SystemVerilog unique, unique0, and priority case
 387     - Added "write_edif" options for edif "flavors"
 388     - Added support for resetall compiler directive
 389     - Added simple C beck-end (bitwise combinatorical only atm)
 390     - Added $_ANDNOT_ and $_ORNOT_ cell types
 391     - Added cell library aliases to "abc -g"
 392     - Added "setundef -anyseq"
 393     - Added "chtype" command
 394     - Added "design -import"
 395     - Added "write_table" command
 396     - Added "read_json" command
 397     - Added "sim" command
 398     - Added "extract_fa" and "extract_reduce" commands
 399     - Added "extract_counter" command
 400     - Added "opt_demorgan" command
 401     - Added support for $size and $bits SystemVerilog functions
 402     - Added "blackbox" command
 403     - Added "ltp" command
 404     - Added support for editline as replacement for readline
 405     - Added warnings for driver-driver conflicts between FFs (and other cells) and constants
 406     - Added "yosys -E" for creating Makefile dependencies files
 407     - Added "synth -noshare"
 408     - Added "memory_nordff"
 409     - Added "setundef -undef -expose -anyconst"
 410     - Added "expose -input"
 411     - Added specify/specparam parser support (simply ignore them)
 412     - Added "write_blif -inames -iattr"
 413     - Added "hierarchy -simcheck"
 414     - Added an option to statically link abc into yosys
 415     - Added protobuf back-end
 416     - Added BLIF parsing support for .conn and .cname
 417     - Added read_verilog error checking for reg/wire/logic misuse
 418     - Added "make coverage" and ENABLE_GCOV build option
 419
 420  * Changes in Yosys APIs
 421     - Added ConstEval defaultval feature
 422     - Added {get,set}_src_attribute() methods on RTLIL::AttrObject
 423     - Added SigSpec::is_fully_ones() and Const::is_fully_ones()
 424     - Added log_file_warning() and log_file_error() functions
 425
 426  * Formal Verification
 427     - Added "write_aiger"
 428     - Added "yosys-smtbmc --aig"
 429     - Added "always <positive_int>" to .smtc format
 430     - Added $cover cell type and support for cover properties
 431     - Added $fair/$live cell type and support for liveness properties
 432     - Added smtbmc support for memory vcd dumping
 433     - Added "chformal" command
 434     - Added "write_smt2 -stbv" and "write_smt2 -stdt"
 435     - Fix equiv_simple, old behavior now available with "equiv_simple -short"
 436     - Change to Yices2 as default SMT solver (it is GPL now)
 437     - Added "yosys-smtbmc --presat" (now default in SymbiYosys)
 438     - Added "yosys-smtbmc --smtc-init --smtc-top --noinit"
 439     - Added a brand new "write_btor" command for BTOR2
 440     - Added clk2fflogic memory support and other improvements
 441     - Added "async memory write" support to write_smt2
 442     - Simulate clock toggling in yosys-smtbmc VCD output
 443     - Added $allseq/$allconst cells for EA-solving
 444     - Make -nordff the default in "prep"
 445     - Added (* gclk *) attribute
 446     - Added "async2sync" pass for single-clock designs with async resets
 447
 448  * Verific support
 449     - Many improvements in Verific front-end
 450     - Added proper handling of concurent SVA properties
 451     - Map "const" and "rand const" to $anyseq/$anyconst
 452     - Added "verific -import -flatten" and "verific -import -extnets"
 453     - Added "verific -vlog-incdir -vlog-define -vlog-libdir"
 454     - Remove PSL support (because PSL has been removed in upstream Verific)
 455     - Improve integration with "hierarchy" command design elaboration
 456     - Added YOSYS_NOVERIFIC for running non-verific test cases with verific bin
 457     - Added simpilied "read" command that automatically uses verific if available
 458     - Added "verific -set-<severity> <msg_id>.."
 459     - Added "verific -work <libname>"
 460
 461  * New back-ends
 462     - Added initial Coolrunner-II support
 463     - Added initial eASIC support
 464     - Added initial ECP5 support
 465
 466  * GreenPAK Support
 467     - Added support for GP_DLATCH, GP_SPI, GP_DCMx, GP_COUNTx, etc.
 468
 469  * iCE40 Support
 470     - Add "synth_ice40 -vpr"
 471     - Add "synth_ice40 -nodffe"
 472     - Add "synth_ice40 -json"
 473     - Add Support for UltraPlus cells
 474
 475  * MAX10 and Cyclone IV Support
 476     - Added initial version of metacommand "synth_intel".
 477     - Improved write_verilog command to produce VQM netlist for Quartus Prime.
 478     - Added support for MAX10 FPGA family synthesis.
 479     - Added support for Cyclone IV family synthesis.
 480     - Added example of implementation for DE2i-150 board.
 481     - Added example of implementation for MAX10 development kit.
 482     - Added LFSR example from Asic World.
 483     - Added "dffinit -highlow" for mapping to Intel primitives
 484
 485
 486 Yosys 0.6 .. Yosys 0.7
 487 ----------------------
 488
 489  * Various
 490     - Added "yosys -D" feature
 491     - Added support for installed plugins in $(DATDIR)/plugins/
 492     - Renamed opt_const to opt_expr
 493     - Renamed opt_share to opt_merge
 494     - Added "prep -flatten" and "synth -flatten"
 495     - Added "prep -auto-top" and "synth -auto-top"
 496     - Using "mfs" and "lutpack" in ABC lut mapping
 497     - Support for abstract modules in chparam
 498     - Cleanup abstract modules at end of "hierarchy -top"
 499     - Added tristate buffer support to iopadmap
 500     - Added opt_expr support for div/mod by power-of-two
 501     - Added "select -assert-min <N> -assert-max <N>"
 502     - Added "attrmvcp" pass
 503     - Added "attrmap" command
 504     - Added "tee +INT -INT"
 505     - Added "zinit" pass
 506     - Added "setparam -type"
 507     - Added "shregmap" pass
 508     - Added "setundef -init"
 509     - Added "nlutmap -assert"
 510     - Added $sop cell type and "abc -sop -I <num> -P <num>"
 511     - Added "dc2" to default ABC scripts
 512     - Added "deminout"
 513     - Added "insbuf" command
 514     - Added "prep -nomem"
 515     - Added "opt_rmdff -keepdc"
 516     - Added "prep -nokeepdc"
 517     - Added initial version of "synth_gowin"
 518     - Added "fsm_expand -full"
 519     - Added support for fsm_encoding="user"
 520     - Many improvements in GreenPAK4 support
 521     - Added black box modules for all Xilinx 7-series lib cells
 522     - Added synth_ice40 support for latches via logic loops
 523     - Fixed ice40_opt lut unmapping, added "ice40_opt -unlut"
 524
 525  * Build System
 526     - Added ABCEXTERNAL and ABCURL make variables
 527     - Added BINDIR, LIBDIR, and DATDIR make variables
 528     - Added PKG_CONFIG make variable
 529     - Added SEED make variable (for "make test")
 530     - Added YOSYS_VER_STR make variable
 531     - Updated min GCC requirement to GCC 4.8
 532     - Updated required Bison version to Bison 3.x
 533
 534  * Internal APIs
 535     - Added ast.h to exported headers
 536     - Added ScriptPass helper class for script-like passes
 537     - Added CellEdgesDatabase API
 538
 539  * Front-ends and Back-ends
 540     - Added filename glob support to all front-ends
 541     - Added avail (black-box) module params to ilang format
 542     - Added $display %m support
 543     - Added support for $stop Verilog system task
 544     - Added support for SystemVerilog packages
 545     - Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b}
 546     - Added support for "active high" and "active low" latches in read_blif and write_blif
 547     - Use init value "2" for all uninitialized FFs in BLIF back-end
 548     - Added "read_blif -sop"
 549     - Added "write_blif -noalias"
 550     - Added various write_blif options for VTR support
 551     - write_json: also write module attributes.
 552     - Added "write_verilog -nodec -nostr -defparam"
 553     - Added "read_verilog -norestrict -assume-asserts"
 554     - Added support for bus interfaces to "read_liberty -lib"
 555     - Added liberty parser support for types within cell decls
 556     - Added "write_verilog -renameprefix -v"
 557     - Added "write_edif -nogndvcc"
 558
 559  * Formal Verification
 560     - Support for hierarchical designs in smt2 back-end
 561     - Yosys-smtbmc: Support for hierarchical VCD dumping
 562     - Added $initstate cell type and vlog function
 563     - Added $anyconst and $anyseq cell types and vlog functions
 564     - Added printing of code loc of failed asserts to yosys-smtbmc
 565     - Added memory_memx pass, "memory -memx", and "prep -memx"
 566     - Added "proc_mux -ifx"
 567     - Added "yosys-smtbmc -g"
 568     - Deprecated "write_smt2 -regs" (by default on now)
 569     - Made "write_smt2 -bv -mem" default, added "write_smt2 -nobv -nomem"
 570     - Added support for memories to smtio.py
 571     - Added "yosys-smtbmc --dump-vlogtb"
 572     - Added "yosys-smtbmc --smtc --dump-smtc"
 573     - Added "yosys-smtbmc --dump-all"
 574     - Added assertpmux command
 575     - Added "yosys-smtbmc --unroll"
 576     - Added $past, $stable, $rose, $fell SVA functions
 577     - Added "yosys-smtbmc --noinfo and --dummy"
 578     - Added "yosys-smtbmc --noincr"
 579     - Added "yosys-smtbmc --cex <filename>"
 580     - Added $ff and $_FF_ cell types
 581     - Added $global_clock verilog syntax support for creating $ff cells
 582     - Added clk2fflogic
 583
 584
 585 Yosys 0.5 .. Yosys 0.6
 586 ----------------------
 587
 588  * Various
 589      - Added Contributor Covenant Code of Conduct
 590      - Various improvements in dict<> and pool<>
 591      - Added hashlib::mfp and refactored SigMap
 592      - Improved support for reals as module parameters
 593      - Various improvements in SMT2 back-end
 594      - Added "keep_hierarchy" attribute
 595      - Verilog front-end: define `BLACKBOX in -lib mode
 596      - Added API for converting internal cells to AIGs
 597      - Added ENABLE_LIBYOSYS Makefile option
 598      - Removed "techmap -share_map" (use "-map +/filename" instead)
 599      - Switched all Python scripts to Python 3
 600      - Added support for $display()/$write() and $finish() to Verilog front-end
 601      - Added "yosys-smtbmc" formal verification flow
 602      - Added options for clang sanitizers to Makefile
 603
 604  * New commands and options
 605      - Added "scc -expect <N> -nofeedback"
 606      - Added "proc_dlatch"
 607      - Added "check"
 608      - Added "select %xe %cie %coe %M %C %R"
 609      - Added "sat -dump_json" (WaveJSON format)
 610      - Added "sat -tempinduct-baseonly -tempinduct-inductonly"
 611      - Added "sat -stepsize" and "sat -tempinduct-step"
 612      - Added "sat -show-regs -show-public -show-all"
 613      - Added "write_json" (Native Yosys JSON format)
 614      - Added "write_blif -attr"
 615      - Added "dffinit"
 616      - Added "chparam"
 617      - Added "muxcover"
 618      - Added "pmuxtree"
 619      - Added memory_bram "make_outreg" feature
 620      - Added "splice -wires"
 621      - Added "dff2dffe -direct-match"
 622      - Added simplemap $lut support
 623      - Added "read_blif"
 624      - Added "opt_share -share_all"
 625      - Added "aigmap"
 626      - Added "write_smt2 -mem -regs -wires"
 627      - Added "memory -nordff"
 628      - Added "write_smv"
 629      - Added "synth -nordff -noalumacc"
 630      - Added "rename -top new_name"
 631      - Added "opt_const -clkinv"
 632      - Added "synth -nofsm"
 633      - Added "miter -assert"
 634      - Added "read_verilog -noautowire"
 635      - Added "read_verilog -nodpi"
 636      - Added "tribuf"
 637      - Added "lut2mux"
 638      - Added "nlutmap"
 639      - Added "qwp"
 640      - Added "test_cell -noeval"
 641      - Added "edgetypes"
 642      - Added "equiv_struct"
 643      - Added "equiv_purge"
 644      - Added "equiv_mark"
 645      - Added "equiv_add -try -cell"
 646      - Added "singleton"
 647      - Added "abc -g -luts"
 648      - Added "torder"
 649      - Added "write_blif -cname"
 650      - Added "submod -copy"
 651      - Added "dffsr2dff"
 652      - Added "stat -liberty"
 653
 654  * Synthesis metacommands
 655      - Various improvements in synth_xilinx
 656      - Added synth_ice40 and synth_greenpak4
 657      - Added "prep" metacommand for "synthesis lite"
 658
 659  * Cell library changes
 660      - Added cell types to "help" system
 661      - Added $meminit cell type
 662      - Added $assume cell type
 663      - Added $_MUX4_, $_MUX8_, and $_MUX16_ cells
 664      - Added $tribuf and $_TBUF_ cell types
 665      - Added read-enable to memory model
 666
 667  * YosysJS
 668      - Various improvements in emscripten build
 669      - Added alternative webworker-based JS API
 670      - Added a few example applications
 671
 672
 673 Yosys 0.4 .. Yosys 0.5
 674 ----------------------
 675
 676  * API changes
 677      - Added log_warning()
 678      - Added eval_select_args() and eval_select_op()
 679      - Added cell->known(), cell->input(portname), cell->output(portname)
 680      - Skip blackbox modules in design->selected_modules()
 681      - Replaced std::map<> and std::set<> with dict<> and pool<>
 682      - New SigSpec::extend() is what used to be SigSpec::extend_u0()
 683      - Added YS_OVERRIDE, YS_FINAL, YS_ATTRIBUTE, YS_NORETURN
 684
 685  * Cell library changes
 686      - Added flip-flops with enable ($dffe etc.)
 687      - Added $equiv cells for equivalence checking framework
 688
 689  * Various
 690      - Updated ABC to hg rev 61ad5f908c03
 691      - Added clock domain partitioning to ABC pass
 692      - Improved plugin building (see "yosys-config --build")
 693      - Added ENABLE_NDEBUG Makefile flag for high-performance builds
 694      - Added "yosys -d", "yosys -L" and other driver improvements
 695      - Added support for multi-bit (array) cell ports to "write_edif"
 696      - Now printing most output to stdout, not stderr
 697      - Added "onehot" attribute (set by "fsm_map")
 698      - Various performance improvements
 699      - Vastly improved Xilinx flow
 700      - Added "make unsintall"
 701
 702  * Equivalence checking
 703      - Added equivalence checking commands:
 704          equiv_make equiv_simple equiv_status
 705          equiv_induct equiv_miter
 706          equiv_add equiv_remove
 707
 708  * Block RAM support:
 709      - Added "memory_bram" command
 710      - Added BRAM support to Xilinx flow
 711
 712  * Other New Commands and Options
 713      - Added "dff2dffe"
 714      - Added "fsm -encfile"
 715      - Added "dfflibmap -prepare"
 716      - Added "write_blid -unbuf -undef -blackbox"
 717      - Added "write_smt2" for writing SMT-LIBv2 files
 718      - Added "test_cell -w -muxdiv"
 719      - Added "select -read"
 720
 721
 722 Yosys 0.3.0 .. Yosys 0.4
 723 ------------------------
 724
 725  * Platform Support
 726      - Added support for mxe-based cross-builds for win32
 727      - Added sourcecode-export as VisualStudio project
 728      - Added experimental EMCC (JavaScript) support
 729
 730  * Verilog Frontend
 731      - Added -sv option for SystemVerilog (and automatic *.sv file support)
 732      - Added support for real-valued constants and constant expressions
 733      - Added support for non-standard "via_celltype" attribute on task/func
 734      - Added support for non-standard "module mod_name(...);" syntax
 735      - Added support for non-standard """ macro bodies
 736      - Added support for array with more than one dimension
 737      - Added support for $readmemh and $readmemb
 738      - Added support for DPI functions
 739
 740  * Changes in internal cell library
 741      - Added $shift and $shiftx cell types
 742      - Added $alu, $lcu, $fa and $macc cell types
 743      - Removed $bu0 and $safe_pmux cell types
 744      - $mem/$memwr WR_EN input is now a per-data-bit enable signal
 745      - Added $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
 746      - Renamed ports of $lut cells (from I->O to A->Y)
 747      - Renamed $_INV_ to $_NOT_
 748
 749  * Changes for simple synthesis flows
 750      - There is now a "synth" command with a recommended default script
 751      - Many improvements in synthesis of arithmetic functions to gates
 752          - Multipliers and adders with many operands are using carry-save adder trees
 753          - Remaining adders are now implemented using Brent-Kung carry look-ahead adders
 754      - Various new high-level optimizations on RTL netlist
 755      - Various improvements in FSM optimization
 756      - Updated ABC to hg 5b5af75f1dda (from 2014-11-07)
 757
 758  * Changes in internal APIs and RTLIL
 759      - Added log_id() and log_cell() helper functions
 760      - Added function-like cell creation helpers
 761      - Added GetSize() function (like .size() but with int)
 762      - Major refactoring of RTLIL::Module and related classes
 763      - Major refactoring of RTLIL::SigSpec and related classes
 764      - Now RTLIL::IdString is essentially an int
 765      - Added macros for code coverage counters
 766      - Added some Makefile magic for pretty make logs
 767      - Added "kernel/yosys.h" with all the core definitions
 768      - Changed a lot of code from FILE* to c++ streams
 769      - Added RTLIL::Monitor API and "trace" command
 770      - Added "Yosys" C++ namespace
 771
 772  * Changes relevant to SAT solving
 773      - Added ezSAT::keep_cnf() and ezSAT::non_incremental()
 774      - Added native ezSAT support for vector shift ops
 775      - Updated MiniSAT to git 37dc6c67e2 (from 2013-09-25)
 776
 777  * New commands (or large improvements to commands)
 778      - Added "synth" command with default script
 779      - Added "share" (finally some real resource sharing)
 780      - Added "memory_share" (reduce number of ports on memories)
 781      - Added "wreduce" and "alumacc" commands
 782      - Added "opt -keepdc -fine -full -fast"
 783      - Added some "test_*" commands
 784
 785  * Various other changes
 786      - Added %D and %c select operators
 787      - Added support for labels in yosys scripts
 788      - Added support for here-documents in yosys scripts
 789      - Support "+/" prefix for files from proc_share_dir
 790      - Added "autoidx" statement to ilang language
 791      - Switched from "yosys-svgviewer" to "xdot"
 792      - Renamed "stdcells.v" to "techmap.v"
 793      - Various bug fixes and small improvements
 794      - Improved welcome and bye messages
 795
 796
 797 Yosys 0.2.0 .. Yosys 0.3.0
 798 --------------------------
 799
 800  * Driver program and overall behavior:
 801      - Added "design -push" and "design -pop"
 802      - Added "tee" command for redirecting log output
 803
 804  * Changes in the internal cell library:
 805      - Added $dlatchsr and $_DLATCHSR_???_ cell types
 806
 807  * Improvements in Verilog frontend:
 808      - Improved support for const functions (case, always, repeat)
 809      - The generate..endgenerate keywords are now optional
 810      - Added support for arrays of module instances
 811      - Added support for "`default_nettype" directive
 812      - Added support for "`line" directive
 813
 814  * Other front- and back-ends:
 815      - Various changes to "write_blif" options
 816      - Various improvements in EDIF backend
 817      - Added "vhdl2verilog" pseudo-front-end
 818      - Added "verific" pseudo-front-end
 819
 820  * Improvements in technology mapping:
 821      - Added support for recursive techmap
 822      - Added CONSTMSK and CONSTVAL features to techmap
 823      - Added _TECHMAP_CONNMAP_*_ feature to techmap
 824      - Added _TECHMAP_REPLACE_ feature to techmap
 825      - Added "connwrappers" command for wrap-extract-unwrap method
 826      - Added "extract -map %<design_name>" feature
 827      - Added "extract -ignore_param ..." and "extract -ignore_parameters"
 828      - Added "techmap -max_iter" option
 829
 830  * Improvements to "eval" and "sat" framework:
 831      - Now include a copy of Minisat (with build fixes applied)
 832      - Switched to Minisat::SimpSolver as SAT back-end
 833      - Added "sat -dump_vcd" feature
 834      - Added "sat -dump_cnf" feature
 835      - Added "sat -initsteps <N>" feature
 836      - Added "freduce -stop <N>" feature
 837      - Added "freduce -dump <prefix>" feature
 838
 839  * Integration with ABC:
 840      - Updated ABC rev to 7600ffb9340c
 841
 842  * Improvements in the internal APIs:
 843      - Added RTLIL::Module::add... helper methods
 844      - Various build fixes for OSX (Darwin) and OpenBSD
 845
 846
 847 Yosys 0.1.0 .. Yosys 0.2.0
 848 --------------------------
 849
 850  * Changes to the driver program:
 851      - Added "yosys -h" and "yosys -H"
 852      - Added support for backslash line continuation in scripts
 853      - Added support for #-comments in same line as command
 854      - Added "echo" and "log" commands
 855
 856  * Improvements in Verilog frontend:
 857      - Added support for local registers in named blocks
 858      - Added support for "case" in "generate" blocks
 859      - Added support for $clog2 system function
 860      - Added support for basic SystemVerilog assert statements
 861      - Added preprocessor support for macro arguments
 862      - Added preprocessor support for `elsif statement
 863      - Added "verilog_defaults" command
 864      - Added read_verilog -icells option
 865      - Added support for constant sizes from parameters
 866      - Added "read_verilog -setattr"
 867      - Added support for function returning 'integer'
 868      - Added limited support for function calls in parameter values
 869      - Added "read_verilog -defer" to suppress evaluation of modules with default parameters
 870
 871  * Other front- and back-ends:
 872      - Added BTOR backend
 873      - Added Liberty frontend
 874
 875  * Improvements in technology mapping:
 876      - The "dfflibmap" command now strongly prefers solutions with
 877            no inverters in clock paths
 878      - The "dfflibmap" command now prefers cells with smaller area
 879      - Added support for multiple -map options to techmap
 880      - Added "dfflibmap" support for //-comments in liberty files
 881      - Added "memory_unpack" command to revert "memory_collect"
 882      - Added standard techmap rule "techmap -share_map pmux2mux.v"
 883      - Added "iopadmap -bits"
 884      - Added "setundef" command
 885      - Added "hilomap" command
 886
 887  * Changes in the internal cell library:
 888      - Major rewrite of simlib.v for better compatibility with other tools
 889      - Added PRIORITY parameter to $memwr cells
 890      - Added TRANSPARENT parameter to $memrd cells
 891      - Added RD_TRANSPARENT parameter to $mem cells
 892      - Added $bu0 cell (always 0-extend, even undef MSB)
 893      - Added $assert cell type
 894      - Added $slice and $concat cell types
 895
 896  * Integration with ABC:
 897      - Updated ABC to hg rev 2058c8ccea68
 898      - Tighter integration of ABC build with Yosys build. The make
 899            targets 'make abc' and 'make install-abc' are now obsolete.
 900      - Added support for passing FFs from one clock domain through ABC
 901      - Now always use BLIF as exchange format with ABC
 902      - Added support for "abc -script +<command_sequence>"
 903      - Improved standard ABC recipe
 904      - Added support for "keep" attribute to abc command
 905      - Added "abc -dff / -clk / -keepff" options
 906
 907  * Improvements to "eval" and "sat" framework:
 908      - Added support for "0" and "~0" in right-hand side -set expressions
 909      - Added "eval -set-undef" and "eval -table"
 910      - Added "sat -set-init" and "sat -set-init-*" for sequential problems
 911      - Added undef support to SAT solver, incl. various new "sat" options
 912      - Added correct support for === and !== for "eval" and "sat"
 913      - Added "sat -tempinduct" (default -seq is now non-induction sequential)
 914      - Added "sat -prove-asserts"
 915      - Complete rewrite of the 'freduce' command
 916      - Added "miter" command
 917      - Added "sat -show-inputs" and "sat -show-outputs"
 918      - Added "sat -ignore_unknown_cells" (now produce an error by default)
 919      - Added "sat -falsify"
 920      - Now "sat -verify" and "sat -falsify" can also be used without "-prove"
 921      - Added "expose" command
 922      - Added support for @<sel_name> to sat and eval signal expressions
 923
 924  * Changes in the 'make test' framework and auxiliary test tools:
 925      - Added autotest.sh -p and -f options
 926      - Replaced autotest.sh ISIM support with XSIM support
 927      - Added test cases for SAT framework
 928
 929  * Added "abbreviated IDs":
 930      - Now $<something>$foo can be abbreviated as $foo.
 931      - Usually this last part is a unique id (from RTLIL::autoidx)
 932      - This abbreviated IDs are now also used in "show" output
 933
 934  * Other changes to selection framework:
 935      - Now */ is optional in */<mode>:<arg> expressions
 936      - Added "select -assert-none" and "select -assert-any"
 937      - Added support for matching modules by attribute (A:<expr>)
 938      - Added "select -none"
 939      - Added support for r:<expr> pattern for matching cell parameters
 940      - Added support for !=, <, <=, >=, > for attribute and parameter matching
 941      - Added support for %s for selecting sub-modules
 942      - Added support for %m for expanding selections to whole modules
 943      - Added support for i:*, o:* and x:* pattern for selecting module ports
 944      - Added support for s:<expr> pattern for matching wire width
 945      - Added support for %a operation to select wire aliases
 946
 947  * Various other changes to commands and options:
 948      - The "ls" command now supports wildcards
 949      - Added "show -pause" and "show -format dot"
 950      - Added "show -color" support for cells
 951      - Added "show -label" and "show -notitle"
 952      - Added "dump -m" and "dump -n"
 953      - Added "history" command
 954      - Added "rename -hide"
 955      - Added "connect" command
 956      - Added "splitnets -driver"
 957      - Added "opt_const -mux_undef"
 958      - Added "opt_const -mux_bool"
 959      - Added "opt_const -undriven"
 960      - Added "opt -mux_undef -mux_bool -undriven -purge"
 961      - Added "hierarchy -libdir"
 962      - Added "hierarchy -purge_lib" (by default now do not remove lib cells)
 963      - Added "delete" command
 964      - Added "dump -append"
 965      - Added "setattr" and "setparam" commands
 966      - Added "design -stash/-copy-from/-copy-to"
 967      - Added "copy" command
 968      - Added "splice" command
 969