CHANGELOG

   1
   2 List of major changes and improvements between releases
   3 =======================================================
   4
   5 Yosys 0.13 .. Yosys 0.13-dev
   6 --------------------------
   7
   8  * Various
   9     - Added $bmux and $demux cells and related optimization patterns.
  10
  11  * New commands and options
  12     - Added "bmuxmap" and "dmuxmap" passes
  13     - Added "-fst" option to "sim" pass for writing FST files
  14     - Added "-r", "-scope", "-start", "-stop", "-at", "-sim", "-sim-gate",
  15       "-sim-gold" options to "sim" pass for co-simulation
  16
  17  * Anlogic support
  18     - Added support for BRAMs
  19
  20 Yosys 0.12 .. Yosys 0.13
  21 --------------------------
  22
  23  * Various
  24     - Use "read" command to parse HDL files from Yosys command-line
  25     - Added "yosys -r <topmodule>" command line option
  26     - write_verilog: dump zero width sigspecs correctly
  27
  28  * SystemVerilog
  29     - Fixed regression preventing the use array querying functions in case
  30       expressions and case item expressions
  31     - Fixed static size casts inadvertently limiting the result width of binary
  32       operations
  33     - Fixed static size casts ignoring expression signedness
  34     - Fixed static size casts not extending unbased unsized literals
  35     - Added automatic `nosync` inference for local variables in `always_comb`
  36       procedures which are always assigned before they are used to avoid errant
  37       latch inference
  38
  39  * New commands and options
  40     - Added "clean_zerowidth" pass
  41
  42  * Verific support
  43     - Add YOSYS to the implicitly defined verilog macros in verific
  44
  45 Yosys 0.11 .. Yosys 0.12
  46 --------------------------
  47
  48  * Various
  49     - Added iopadmap native support for negative-polarity output enable
  50     - ABC update
  51
  52  * SystemVerilog
  53     - Support parameters using struct as a wiretype
  54
  55  * New commands and options
  56     - Added "-genlib" option to "abc" pass
  57     - Added "sta" very crude static timing analysis pass
  58
  59  * Verific support
  60     - Fixed memory block size in import
  61
  62  * New back-ends
  63     - Added support for GateMate FPGA from Cologne Chip AG
  64
  65  * Intel ALM support
  66     - Added preliminary Arria V support
  67
  68
  69 Yosys 0.10 .. Yosys 0.11
  70 --------------------------
  71
  72  * Various
  73     - Added $aldff and $aldffe (flip-flops with async load) cells
  74
  75  * SystemVerilog
  76     - Fixed an issue which prevented writing directly to a memory word via a
  77       connection to an output port
  78     - Fixed an issue which prevented unbased unsized literals (e.g., `'1`) from
  79       filling the width of a cell input
  80     - Fixed an issue where connecting a slice covering the entirety of a signed
  81       signal to a cell input would cause a failed assertion
  82
  83  * Verific support
  84     - Importer support for {PRIM,WIDE_OPER}_DFF
  85     - Importer support for PRIM_BUFIF1
  86     - Option to use Verific without VHDL support
  87     - Importer support for {PRIM,WIDE_OPER}_DLATCH{,RS}
  88     - Added -cfg option for getting/setting Verific runtime flags
  89
  90 Yosys 0.9 .. Yosys 0.10
  91 --------------------------
  92
  93  * Various
  94     - Added automatic gzip decompression for frontends
  95     - Added $_NMUX_ cell type
  96     - Added automatic gzip compression (based on filename extension) for backends
  97     - Improve attribute and parameter encoding in JSON to avoid ambiguities between
  98       bit vectors and strings containing [01xz]*
  99     - Improvements in pmgen: subpattern and recursive matches
 100     - Support explicit FIRRTL properties
 101     - Improvements in pmgen: slices, choices, define, generate
 102     - Added "_TECHMAP_WIREINIT_*_" parameter and "_TECHMAP_REMOVEINIT_*_" wire for "techmap" pass
 103     - Added +/mul2dsp.v for decomposing wide multipliers to custom-sized ones
 104     - Added new frontend: rpc
 105     - Added --version and -version as aliases for -V
 106     - Improve yosys-smtbmc "solver not found" handling
 107     - Improved support of $readmem[hb] Memory Content File inclusion
 108     - Added CXXRTL backend
 109     - Use YosysHQ/abc instead of upstream berkeley-abc/abc
 110     - Added WASI platform support.
 111     - Added extmodule support to firrtl backend
 112     - Added $divfloor and $modfloor cells
 113     - Added $adffe, $dffsre, $sdff, $sdffe, $sdffce, $adlatch cells
 114     - Added "_TECHMAP_CELLNAME_" parameter for "techmap" pass
 115     - Added firrtl backend support for generic parameters in blackbox components
 116     - Added $meminit_v2 cells (with support for write mask)
 117     - Added $mem_v2, $memrd_v2, $memwr_v2, with the following features:
 118       - write priority masks, per write/write port pair
 119       - transparency and undefined collision behavior masks, per read/write port pair
 120       - read port reset and initialization
 121       - wide ports (accessing a naturally aligned power-of-two number of memory cells)
 122
 123  * New commands and options
 124     - Added "write_xaiger" backend
 125     - Added "read_xaiger"
 126     - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only)
 127     - Added "synth -abc9" (experimental)
 128     - Added "script -scriptwire"
 129     - Added "clkbufmap" pass
 130     - Added "extractinv" pass and "invertible_pin" attribute
 131     - Added "proc_clean -quiet"
 132     - Added "proc_prune" pass
 133     - Added "stat -tech cmos"
 134     - Added "opt_share" pass, run as part of "opt -full"
 135     - Added "-match-init" option to "dff2dffs" pass
 136     - Added "equiv_opt -multiclock"
 137     - Added "techmap_autopurge" support to techmap
 138     - Added "add -mod <modname[s]>"
 139     - Added "paramap" pass
 140     - Added "portlist" command
 141     - Added "check -mapped"
 142     - Added "check -allow-tbuf"
 143     - Added "autoname" pass
 144     - Added "write_verilog -extmem"
 145     - Added "opt_mem" pass
 146     - Added "scratchpad" pass
 147     - Added "fminit" pass
 148     - Added "opt_lut_ins" pass
 149     - Added "logger" pass
 150     - Added "show -nobg"
 151     - Added "exec" command
 152     - Added "design -delete"
 153     - Added "design -push-copy"
 154     - Added "qbfsat" command
 155     - Added "select -unset"
 156     - Added "dfflegalize" pass
 157     - Removed "opt_expr -clkinv" option, made it the default
 158     - Added "proc -nomux
 159     - Merged "dffsr2dff", "opt_rmdff", "dff2dffe", "dff2dffs", "peepopt.dffmux" passes into a new "opt_dff" pass
 160
 161  * SystemVerilog
 162     - Added checking of always block types (always_comb, always_latch and always_ff)
 163     - Added support for wildcard port connections (.*)
 164     - Added support for enum typedefs
 165     - Added support for structs and packed unions.
 166     - Allow constant function calls in for loops and generate if and case
 167     - Added support for static cast
 168     - Added support for logic typed parameters
 169     - Fixed generate scoping issues
 170     - Added support for real-valued parameters
 171     - Allow localparams in constant functions
 172     - Module name scope support
 173     - Support recursive functions using ternary expressions
 174     - Extended support for integer types
 175     - Support for parameters without default values
 176     - Allow globals in one file to depend on globals in another
 177     - Added support for: *=, /=, %=, <<=, >>=, <<<=, >>>=
 178     - Added support for parsing the 'bind' construct
 179     - support declaration in procedural for initialization
 180     - support declaration in generate for initialization
 181     - Support wand and wor of data types
 182
 183  * Verific support
 184     - Added "verific -L"
 185     - Add Verific SVA support for "always" properties
 186     - Add Verific support for SVA nexttime properties
 187     - Improve handling of verific primitives in "verific -import -V" mode
 188     - Import attributes for wires
 189     - Support VHDL enums
 190     - Added support for command files
 191
 192  * New back-ends
 193     - Added initial EFINIX support
 194     - Added Intel ALM: alternative synthesis for Intel FPGAs
 195     - Added initial Nexus support
 196     - Added initial MachXO2 support
 197     - Added initial QuickLogic PolarPro 3 support
 198
 199  * ECP5 support
 200     - Renamed labels/options in synth_ecp5 (e.g. dram -> map_lutram; -nodram -> -nolutram)
 201     - Added "synth_ecp5 -abc9" (experimental)
 202     - Added "synth_ecp5 -nowidelut"
 203     - "synth_ecp5" to now infer DSP blocks (-nodsp to disable, experimental)
 204
 205  * iCE40 support
 206     - Added "synth_ice40 -abc9" (experimental)
 207     - Added "synth_ice40 -device"
 208     - Renamed labels/options in synth_ice40 (e.g. dram -> map_lutram; -nodram -> -nolutram)
 209     - Added "ice40_wrapcarry" to encapsulate SB_LUT+SB_CARRY pairs for techmapping
 210     - Removed "ice40_unlut"
 211     - Added "ice40_dsp" for Lattice iCE40 DSP packing
 212     - "synth_ice40 -dsp" to infer DSP blocks
 213
 214  * Xilinx support
 215     - Added "synth_xilinx -abc9" (experimental)
 216     - Added "synth_xilinx -nocarry"
 217     - Added "synth_xilinx -nowidelut"
 218     - "synth_xilinx" to now infer wide multiplexers (-widemux <min> to enable)
 219     - Renamed labels/options in synth_xilinx (e.g. dram -> map_lutram; -nodram -> -nolutram)
 220     - Added "synth_xilinx -family xc6s" for Spartan 6 support (experimental)
 221     - Added "synth_xilinx -ise" (experimental)
 222     - Added "synth_xilinx -iopad"
 223     - "synth_xilinx" now automatically inserts clock buffers (add -noclkbuf to disable)
 224     - Added "xilinx_srl" for Xilinx shift register extraction
 225     - Removed "shregmap -tech xilinx" (superseded by "xilinx_srl")
 226     - Added "xilinx_dsp" for Xilinx DSP packing
 227     - "synth_xilinx" to now infer DSP blocks (-nodsp to disable)
 228     - Added latch support to synth_xilinx
 229     - Added support for flip-flops with synchronous reset to synth_xilinx
 230     - Added support for flip-flops with reset and enable to synth_xilinx
 231     - Added "xilinx_dffopt" pass
 232     - Added "synth_xilinx -dff"
 233
 234  * Intel support
 235     - Renamed labels in synth_intel (e.g. bram -> map_bram)
 236     - synth_intel: cyclone10 -> cyclone10lp, a10gx -> arria10gx
 237     - Added "intel_alm -abc9" (experimental)
 238
 239  * CoolRunner2 support
 240     - Separate and improve buffer cell insertion pass
 241     - Use extract_counter to optimize counters
 242
 243 Yosys 0.8 .. Yosys 0.9
 244 ----------------------
 245
 246  * Various
 247     - Many bugfixes and small improvements
 248     - Added support for SystemVerilog interfaces and modports
 249     - Added "write_edif -attrprop"
 250     - Added "opt_lut" pass
 251     - Added "gate2lut.v" techmap rule
 252     - Added "rename -src"
 253     - Added "equiv_opt" pass
 254     - Added "flowmap" LUT mapping pass
 255     - Added "rename -wire" to rename cells based on the wires they drive
 256     - Added "bugpoint" for creating minimised testcases
 257     - Added "write_edif -gndvccy"
 258     - "write_verilog" to escape Verilog keywords
 259     - Fixed sign handling of real constants
 260     - "write_verilog" to write initial statement for initial flop state
 261     - Added pmgen pattern matcher generator
 262     - Fixed opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_
 263     - Added "setundef -params" to replace undefined cell parameters
 264     - Renamed "yosys -D" to "yosys -U", added "yosys -D" to set Verilog defines
 265     - Fixed handling of defparam when default_nettype is none
 266     - Fixed "wreduce" flipflop handling
 267     - Fixed FIRRTL to Verilog process instance subfield assignment
 268     - Added "write_verilog -siminit"
 269     - Several fixes and improvements for mem2reg memories
 270     - Fixed handling of task output ports in clocked always blocks
 271     - Improved handling of and-with-1 and or-with-0 in "opt_expr"
 272     - Added "read_aiger" frontend
 273     - Added "mutate" pass
 274     - Added "hdlname" attribute
 275     - Added "rename -output"
 276     - Added "read_ilang -lib"
 277     - Improved "proc" full_case detection and handling
 278     - Added "whitebox" and "lib_whitebox" attributes
 279     - Added "read_verilog -nowb", "flatten -wb" and "wbflip"
 280     - Added Python bindings and support for Python plug-ins
 281     - Added "pmux2shiftx"
 282     - Added log_debug framework for reduced default verbosity
 283     - Improved "opt_expr" and "opt_clean" handling of (partially) undriven and/or unused wires
 284     - Added "peepopt" peephole optimisation pass using pmgen
 285     - Added approximate support for SystemVerilog "var" keyword
 286     - Added parsing of "specify" blocks into $specrule and $specify[23]
 287     - Added support for attributes on parameters and localparams
 288     - Added support for parsing attributes on port connections
 289     - Added "wreduce -keepdc"
 290     - Added support for optimising $dffe and $_DFFE_* cells in "opt_rmdff"
 291     - Added Verilog wand/wor wire type support
 292     - Added support for elaboration system tasks
 293     - Added "muxcover -mux{4,8,16}=<cost>"
 294     - Added "muxcover -dmux=<cost>"
 295     - Added "muxcover -nopartial"
 296     - Added "muxpack" pass
 297     - Added "pmux2shiftx -norange"
 298     - Added support for "~" in filename parsing
 299     - Added "read_verilog -pwires" feature to turn parameters into wires
 300     - Fixed sign extension of unsized constants with 'bx and 'bz MSB
 301     - Fixed genvar to be a signed type
 302     - Added support for attributes on case rules
 303     - Added "upto" and "offset" to JSON frontend and backend
 304     - Several liberty file parser improvements
 305     - Fixed handling of more complex BRAM patterns
 306     - Add "write_aiger -I -O -B"
 307
 308  * Formal Verification
 309     - Added $changed support to read_verilog
 310     - Added "read_verilog -noassert -noassume -assert-assumes"
 311     - Added btor ops for $mul, $div, $mod and $concat
 312     - Added yosys-smtbmc support for btor witnesses
 313     - Added "supercover" pass
 314     - Fixed $global_clock handling vs autowire
 315     - Added $dffsr support to "async2sync"
 316     - Added "fmcombine" pass
 317     - Added memory init support in "write_btor"
 318     - Added "cutpoint" pass
 319     - Changed "ne" to "neq" in btor2 output
 320     - Added support for SVA "final" keyword
 321     - Added "fmcombine -initeq -anyeq"
 322     - Added timescale and generated-by header to yosys-smtbmc vcd output
 323     - Improved BTOR2 handling of undriven wires
 324
 325  * Verific support
 326     - Enabled Verific flags vhdl_support_variable_slice and veri_elaborate_top_level_modules_having_interface_ports
 327     - Improved support for asymmetric memories
 328     - Added "verific -chparam"
 329     - Fixed "verific -extnets" for more complex situations
 330     - Added "read -verific" and "read -noverific"
 331     - Added "hierarchy -chparam"
 332
 333  * New back-ends
 334     - Added initial Anlogic support
 335     - Added initial SmartFusion2 and IGLOO2 support
 336
 337  * ECP5 support
 338     - Added "synth_ecp5 -nowidelut"
 339     - Added BRAM inference support to "synth_ecp5"
 340     - Added support for transforming Diamond IO and flipflop primitives
 341
 342  * iCE40 support
 343     - Added "ice40_unlut" pass
 344     - Added "synth_ice40 -relut"
 345     - Added "synth_ice40 -noabc"
 346     - Added "synth_ice40 -dffe_min_ce_use"
 347     - Added DSP inference support using pmgen
 348     - Added support for initialising BRAM primitives from a file
 349     - Added iCE40 Ultra RGB LED driver cells
 350
 351  * Xilinx support
 352     - Use "write_edif -pvector bra" for Xilinx EDIF files
 353     - Fixes for VPR place and route support with "synth_xilinx"
 354     - Added more cell simulation models
 355     - Added "synth_xilinx -family"
 356     - Added "stat -tech xilinx" to estimate logic cell usage
 357     - Added "synth_xilinx -nocarry"
 358     - Added "synth_xilinx -nowidelut"
 359     - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
 360     - Added support for mapping RAM32X1D
 361
 362 Yosys 0.7 .. Yosys 0.8
 363 ----------------------
 364
 365  * Various
 366     - Many bugfixes and small improvements
 367     - Strip debug symbols from installed binary
 368     - Replace -ignore_redef with -[no]overwrite in front-ends
 369     - Added write_verilog hex dump support, add -nohex option
 370     - Added "write_verilog -decimal"
 371     - Added "scc -set_attr"
 372     - Added "verilog_defines" command
 373     - Remember defines from one read_verilog to next
 374     - Added support for hierarchical defparam
 375     - Added FIRRTL back-end
 376     - Improved ABC default scripts
 377     - Added "design -reset-vlog"
 378     - Added "yosys -W regex", "yosys -w regex", and "yosys -e regex"
 379     - Added Verilog $rtoi and $itor support
 380     - Added "check -initdrv"
 381     - Added "read_blif -wideports"
 382     - Added support for SystemVerilog "++" and "--" operators
 383     - Added support for SystemVerilog unique, unique0, and priority case
 384     - Added "write_edif" options for edif "flavors"
 385     - Added support for resetall compiler directive
 386     - Added simple C beck-end (bitwise combinatorical only atm)
 387     - Added $_ANDNOT_ and $_ORNOT_ cell types
 388     - Added cell library aliases to "abc -g"
 389     - Added "setundef -anyseq"
 390     - Added "chtype" command
 391     - Added "design -import"
 392     - Added "write_table" command
 393     - Added "read_json" command
 394     - Added "sim" command
 395     - Added "extract_fa" and "extract_reduce" commands
 396     - Added "extract_counter" command
 397     - Added "opt_demorgan" command
 398     - Added support for $size and $bits SystemVerilog functions
 399     - Added "blackbox" command
 400     - Added "ltp" command
 401     - Added support for editline as replacement for readline
 402     - Added warnings for driver-driver conflicts between FFs (and other cells) and constants
 403     - Added "yosys -E" for creating Makefile dependencies files
 404     - Added "synth -noshare"
 405     - Added "memory_nordff"
 406     - Added "setundef -undef -expose -anyconst"
 407     - Added "expose -input"
 408     - Added specify/specparam parser support (simply ignore them)
 409     - Added "write_blif -inames -iattr"
 410     - Added "hierarchy -simcheck"
 411     - Added an option to statically link abc into yosys
 412     - Added protobuf back-end
 413     - Added BLIF parsing support for .conn and .cname
 414     - Added read_verilog error checking for reg/wire/logic misuse
 415     - Added "make coverage" and ENABLE_GCOV build option
 416
 417  * Changes in Yosys APIs
 418     - Added ConstEval defaultval feature
 419     - Added {get,set}_src_attribute() methods on RTLIL::AttrObject
 420     - Added SigSpec::is_fully_ones() and Const::is_fully_ones()
 421     - Added log_file_warning() and log_file_error() functions
 422
 423  * Formal Verification
 424     - Added "write_aiger"
 425     - Added "yosys-smtbmc --aig"
 426     - Added "always <positive_int>" to .smtc format
 427     - Added $cover cell type and support for cover properties
 428     - Added $fair/$live cell type and support for liveness properties
 429     - Added smtbmc support for memory vcd dumping
 430     - Added "chformal" command
 431     - Added "write_smt2 -stbv" and "write_smt2 -stdt"
 432     - Fix equiv_simple, old behavior now available with "equiv_simple -short"
 433     - Change to Yices2 as default SMT solver (it is GPL now)
 434     - Added "yosys-smtbmc --presat" (now default in SymbiYosys)
 435     - Added "yosys-smtbmc --smtc-init --smtc-top --noinit"
 436     - Added a brand new "write_btor" command for BTOR2
 437     - Added clk2fflogic memory support and other improvements
 438     - Added "async memory write" support to write_smt2
 439     - Simulate clock toggling in yosys-smtbmc VCD output
 440     - Added $allseq/$allconst cells for EA-solving
 441     - Make -nordff the default in "prep"
 442     - Added (* gclk *) attribute
 443     - Added "async2sync" pass for single-clock designs with async resets
 444
 445  * Verific support
 446     - Many improvements in Verific front-end
 447     - Added proper handling of concurent SVA properties
 448     - Map "const" and "rand const" to $anyseq/$anyconst
 449     - Added "verific -import -flatten" and "verific -import -extnets"
 450     - Added "verific -vlog-incdir -vlog-define -vlog-libdir"
 451     - Remove PSL support (because PSL has been removed in upstream Verific)
 452     - Improve integration with "hierarchy" command design elaboration
 453     - Added YOSYS_NOVERIFIC for running non-verific test cases with verific bin
 454     - Added simpilied "read" command that automatically uses verific if available
 455     - Added "verific -set-<severity> <msg_id>.."
 456     - Added "verific -work <libname>"
 457
 458  * New back-ends
 459     - Added initial Coolrunner-II support
 460     - Added initial eASIC support
 461     - Added initial ECP5 support
 462
 463  * GreenPAK Support
 464     - Added support for GP_DLATCH, GP_SPI, GP_DCMx, GP_COUNTx, etc.
 465
 466  * iCE40 Support
 467     - Add "synth_ice40 -vpr"
 468     - Add "synth_ice40 -nodffe"
 469     - Add "synth_ice40 -json"
 470     - Add Support for UltraPlus cells
 471
 472  * MAX10 and Cyclone IV Support
 473     - Added initial version of metacommand "synth_intel".
 474     - Improved write_verilog command to produce VQM netlist for Quartus Prime.
 475     - Added support for MAX10 FPGA family synthesis.
 476     - Added support for Cyclone IV family synthesis.
 477     - Added example of implementation for DE2i-150 board.
 478     - Added example of implementation for MAX10 development kit.
 479     - Added LFSR example from Asic World.
 480     - Added "dffinit -highlow" for mapping to Intel primitives
 481
 482
 483 Yosys 0.6 .. Yosys 0.7
 484 ----------------------
 485
 486  * Various
 487     - Added "yosys -D" feature
 488     - Added support for installed plugins in $(DATDIR)/plugins/
 489     - Renamed opt_const to opt_expr
 490     - Renamed opt_share to opt_merge
 491     - Added "prep -flatten" and "synth -flatten"
 492     - Added "prep -auto-top" and "synth -auto-top"
 493     - Using "mfs" and "lutpack" in ABC lut mapping
 494     - Support for abstract modules in chparam
 495     - Cleanup abstract modules at end of "hierarchy -top"
 496     - Added tristate buffer support to iopadmap
 497     - Added opt_expr support for div/mod by power-of-two
 498     - Added "select -assert-min <N> -assert-max <N>"
 499     - Added "attrmvcp" pass
 500     - Added "attrmap" command
 501     - Added "tee +INT -INT"
 502     - Added "zinit" pass
 503     - Added "setparam -type"
 504     - Added "shregmap" pass
 505     - Added "setundef -init"
 506     - Added "nlutmap -assert"
 507     - Added $sop cell type and "abc -sop -I <num> -P <num>"
 508     - Added "dc2" to default ABC scripts
 509     - Added "deminout"
 510     - Added "insbuf" command
 511     - Added "prep -nomem"
 512     - Added "opt_rmdff -keepdc"
 513     - Added "prep -nokeepdc"
 514     - Added initial version of "synth_gowin"
 515     - Added "fsm_expand -full"
 516     - Added support for fsm_encoding="user"
 517     - Many improvements in GreenPAK4 support
 518     - Added black box modules for all Xilinx 7-series lib cells
 519     - Added synth_ice40 support for latches via logic loops
 520     - Fixed ice40_opt lut unmapping, added "ice40_opt -unlut"
 521
 522  * Build System
 523     - Added ABCEXTERNAL and ABCURL make variables
 524     - Added BINDIR, LIBDIR, and DATDIR make variables
 525     - Added PKG_CONFIG make variable
 526     - Added SEED make variable (for "make test")
 527     - Added YOSYS_VER_STR make variable
 528     - Updated min GCC requirement to GCC 4.8
 529     - Updated required Bison version to Bison 3.x
 530
 531  * Internal APIs
 532     - Added ast.h to exported headers
 533     - Added ScriptPass helper class for script-like passes
 534     - Added CellEdgesDatabase API
 535
 536  * Front-ends and Back-ends
 537     - Added filename glob support to all front-ends
 538     - Added avail (black-box) module params to ilang format
 539     - Added $display %m support
 540     - Added support for $stop Verilog system task
 541     - Added support for SystemVerilog packages
 542     - Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b}
 543     - Added support for "active high" and "active low" latches in read_blif and write_blif
 544     - Use init value "2" for all uninitialized FFs in BLIF back-end
 545     - Added "read_blif -sop"
 546     - Added "write_blif -noalias"
 547     - Added various write_blif options for VTR support
 548     - write_json: also write module attributes.
 549     - Added "write_verilog -nodec -nostr -defparam"
 550     - Added "read_verilog -norestrict -assume-asserts"
 551     - Added support for bus interfaces to "read_liberty -lib"
 552     - Added liberty parser support for types within cell decls
 553     - Added "write_verilog -renameprefix -v"
 554     - Added "write_edif -nogndvcc"
 555
 556  * Formal Verification
 557     - Support for hierarchical designs in smt2 back-end
 558     - Yosys-smtbmc: Support for hierarchical VCD dumping
 559     - Added $initstate cell type and vlog function
 560     - Added $anyconst and $anyseq cell types and vlog functions
 561     - Added printing of code loc of failed asserts to yosys-smtbmc
 562     - Added memory_memx pass, "memory -memx", and "prep -memx"
 563     - Added "proc_mux -ifx"
 564     - Added "yosys-smtbmc -g"
 565     - Deprecated "write_smt2 -regs" (by default on now)
 566     - Made "write_smt2 -bv -mem" default, added "write_smt2 -nobv -nomem"
 567     - Added support for memories to smtio.py
 568     - Added "yosys-smtbmc --dump-vlogtb"
 569     - Added "yosys-smtbmc --smtc --dump-smtc"
 570     - Added "yosys-smtbmc --dump-all"
 571     - Added assertpmux command
 572     - Added "yosys-smtbmc --unroll"
 573     - Added $past, $stable, $rose, $fell SVA functions
 574     - Added "yosys-smtbmc --noinfo and --dummy"
 575     - Added "yosys-smtbmc --noincr"
 576     - Added "yosys-smtbmc --cex <filename>"
 577     - Added $ff and $_FF_ cell types
 578     - Added $global_clock verilog syntax support for creating $ff cells
 579     - Added clk2fflogic
 580
 581
 582 Yosys 0.5 .. Yosys 0.6
 583 ----------------------
 584
 585  * Various
 586      - Added Contributor Covenant Code of Conduct
 587      - Various improvements in dict<> and pool<>
 588      - Added hashlib::mfp and refactored SigMap
 589      - Improved support for reals as module parameters
 590      - Various improvements in SMT2 back-end
 591      - Added "keep_hierarchy" attribute
 592      - Verilog front-end: define `BLACKBOX in -lib mode
 593      - Added API for converting internal cells to AIGs
 594      - Added ENABLE_LIBYOSYS Makefile option
 595      - Removed "techmap -share_map" (use "-map +/filename" instead)
 596      - Switched all Python scripts to Python 3
 597      - Added support for $display()/$write() and $finish() to Verilog front-end
 598      - Added "yosys-smtbmc" formal verification flow
 599      - Added options for clang sanitizers to Makefile
 600
 601  * New commands and options
 602      - Added "scc -expect <N> -nofeedback"
 603      - Added "proc_dlatch"
 604      - Added "check"
 605      - Added "select %xe %cie %coe %M %C %R"
 606      - Added "sat -dump_json" (WaveJSON format)
 607      - Added "sat -tempinduct-baseonly -tempinduct-inductonly"
 608      - Added "sat -stepsize" and "sat -tempinduct-step"
 609      - Added "sat -show-regs -show-public -show-all"
 610      - Added "write_json" (Native Yosys JSON format)
 611      - Added "write_blif -attr"
 612      - Added "dffinit"
 613      - Added "chparam"
 614      - Added "muxcover"
 615      - Added "pmuxtree"
 616      - Added memory_bram "make_outreg" feature
 617      - Added "splice -wires"
 618      - Added "dff2dffe -direct-match"
 619      - Added simplemap $lut support
 620      - Added "read_blif"
 621      - Added "opt_share -share_all"
 622      - Added "aigmap"
 623      - Added "write_smt2 -mem -regs -wires"
 624      - Added "memory -nordff"
 625      - Added "write_smv"
 626      - Added "synth -nordff -noalumacc"
 627      - Added "rename -top new_name"
 628      - Added "opt_const -clkinv"
 629      - Added "synth -nofsm"
 630      - Added "miter -assert"
 631      - Added "read_verilog -noautowire"
 632      - Added "read_verilog -nodpi"
 633      - Added "tribuf"
 634      - Added "lut2mux"
 635      - Added "nlutmap"
 636      - Added "qwp"
 637      - Added "test_cell -noeval"
 638      - Added "edgetypes"
 639      - Added "equiv_struct"
 640      - Added "equiv_purge"
 641      - Added "equiv_mark"
 642      - Added "equiv_add -try -cell"
 643      - Added "singleton"
 644      - Added "abc -g -luts"
 645      - Added "torder"
 646      - Added "write_blif -cname"
 647      - Added "submod -copy"
 648      - Added "dffsr2dff"
 649      - Added "stat -liberty"
 650
 651  * Synthesis metacommands
 652      - Various improvements in synth_xilinx
 653      - Added synth_ice40 and synth_greenpak4
 654      - Added "prep" metacommand for "synthesis lite"
 655
 656  * Cell library changes
 657      - Added cell types to "help" system
 658      - Added $meminit cell type
 659      - Added $assume cell type
 660      - Added $_MUX4_, $_MUX8_, and $_MUX16_ cells
 661      - Added $tribuf and $_TBUF_ cell types
 662      - Added read-enable to memory model
 663
 664  * YosysJS
 665      - Various improvements in emscripten build
 666      - Added alternative webworker-based JS API
 667      - Added a few example applications
 668
 669
 670 Yosys 0.4 .. Yosys 0.5
 671 ----------------------
 672
 673  * API changes
 674      - Added log_warning()
 675      - Added eval_select_args() and eval_select_op()
 676      - Added cell->known(), cell->input(portname), cell->output(portname)
 677      - Skip blackbox modules in design->selected_modules()
 678      - Replaced std::map<> and std::set<> with dict<> and pool<>
 679      - New SigSpec::extend() is what used to be SigSpec::extend_u0()
 680      - Added YS_OVERRIDE, YS_FINAL, YS_ATTRIBUTE, YS_NORETURN
 681
 682  * Cell library changes
 683      - Added flip-flops with enable ($dffe etc.)
 684      - Added $equiv cells for equivalence checking framework
 685
 686  * Various
 687      - Updated ABC to hg rev 61ad5f908c03
 688      - Added clock domain partitioning to ABC pass
 689      - Improved plugin building (see "yosys-config --build")
 690      - Added ENABLE_NDEBUG Makefile flag for high-performance builds
 691      - Added "yosys -d", "yosys -L" and other driver improvements
 692      - Added support for multi-bit (array) cell ports to "write_edif"
 693      - Now printing most output to stdout, not stderr
 694      - Added "onehot" attribute (set by "fsm_map")
 695      - Various performance improvements
 696      - Vastly improved Xilinx flow
 697      - Added "make unsintall"
 698
 699  * Equivalence checking
 700      - Added equivalence checking commands:
 701          equiv_make equiv_simple equiv_status
 702          equiv_induct equiv_miter
 703          equiv_add equiv_remove
 704
 705  * Block RAM support:
 706      - Added "memory_bram" command
 707      - Added BRAM support to Xilinx flow
 708
 709  * Other New Commands and Options
 710      - Added "dff2dffe"
 711      - Added "fsm -encfile"
 712      - Added "dfflibmap -prepare"
 713      - Added "write_blid -unbuf -undef -blackbox"
 714      - Added "write_smt2" for writing SMT-LIBv2 files
 715      - Added "test_cell -w -muxdiv"
 716      - Added "select -read"
 717
 718
 719 Yosys 0.3.0 .. Yosys 0.4
 720 ------------------------
 721
 722  * Platform Support
 723      - Added support for mxe-based cross-builds for win32
 724      - Added sourcecode-export as VisualStudio project
 725      - Added experimental EMCC (JavaScript) support
 726
 727  * Verilog Frontend
 728      - Added -sv option for SystemVerilog (and automatic *.sv file support)
 729      - Added support for real-valued constants and constant expressions
 730      - Added support for non-standard "via_celltype" attribute on task/func
 731      - Added support for non-standard "module mod_name(...);" syntax
 732      - Added support for non-standard """ macro bodies
 733      - Added support for array with more than one dimension
 734      - Added support for $readmemh and $readmemb
 735      - Added support for DPI functions
 736
 737  * Changes in internal cell library
 738      - Added $shift and $shiftx cell types
 739      - Added $alu, $lcu, $fa and $macc cell types
 740      - Removed $bu0 and $safe_pmux cell types
 741      - $mem/$memwr WR_EN input is now a per-data-bit enable signal
 742      - Added $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
 743      - Renamed ports of $lut cells (from I->O to A->Y)
 744      - Renamed $_INV_ to $_NOT_
 745
 746  * Changes for simple synthesis flows
 747      - There is now a "synth" command with a recommended default script
 748      - Many improvements in synthesis of arithmetic functions to gates
 749          - Multipliers and adders with many operands are using carry-save adder trees
 750          - Remaining adders are now implemented using Brent-Kung carry look-ahead adders
 751      - Various new high-level optimizations on RTL netlist
 752      - Various improvements in FSM optimization
 753      - Updated ABC to hg 5b5af75f1dda (from 2014-11-07)
 754
 755  * Changes in internal APIs and RTLIL
 756      - Added log_id() and log_cell() helper functions
 757      - Added function-like cell creation helpers
 758      - Added GetSize() function (like .size() but with int)
 759      - Major refactoring of RTLIL::Module and related classes
 760      - Major refactoring of RTLIL::SigSpec and related classes
 761      - Now RTLIL::IdString is essentially an int
 762      - Added macros for code coverage counters
 763      - Added some Makefile magic for pretty make logs
 764      - Added "kernel/yosys.h" with all the core definitions
 765      - Changed a lot of code from FILE* to c++ streams
 766      - Added RTLIL::Monitor API and "trace" command
 767      - Added "Yosys" C++ namespace
 768
 769  * Changes relevant to SAT solving
 770      - Added ezSAT::keep_cnf() and ezSAT::non_incremental()
 771      - Added native ezSAT support for vector shift ops
 772      - Updated MiniSAT to git 37dc6c67e2 (from 2013-09-25)
 773
 774  * New commands (or large improvements to commands)
 775      - Added "synth" command with default script
 776      - Added "share" (finally some real resource sharing)
 777      - Added "memory_share" (reduce number of ports on memories)
 778      - Added "wreduce" and "alumacc" commands
 779      - Added "opt -keepdc -fine -full -fast"
 780      - Added some "test_*" commands
 781
 782  * Various other changes
 783      - Added %D and %c select operators
 784      - Added support for labels in yosys scripts
 785      - Added support for here-documents in yosys scripts
 786      - Support "+/" prefix for files from proc_share_dir
 787      - Added "autoidx" statement to ilang language
 788      - Switched from "yosys-svgviewer" to "xdot"
 789      - Renamed "stdcells.v" to "techmap.v"
 790      - Various bug fixes and small improvements
 791      - Improved welcome and bye messages
 792
 793
 794 Yosys 0.2.0 .. Yosys 0.3.0
 795 --------------------------
 796
 797  * Driver program and overall behavior:
 798      - Added "design -push" and "design -pop"
 799      - Added "tee" command for redirecting log output
 800
 801  * Changes in the internal cell library:
 802      - Added $dlatchsr and $_DLATCHSR_???_ cell types
 803
 804  * Improvements in Verilog frontend:
 805      - Improved support for const functions (case, always, repeat)
 806      - The generate..endgenerate keywords are now optional
 807      - Added support for arrays of module instances
 808      - Added support for "`default_nettype" directive
 809      - Added support for "`line" directive
 810
 811  * Other front- and back-ends:
 812      - Various changes to "write_blif" options
 813      - Various improvements in EDIF backend
 814      - Added "vhdl2verilog" pseudo-front-end
 815      - Added "verific" pseudo-front-end
 816
 817  * Improvements in technology mapping:
 818      - Added support for recursive techmap
 819      - Added CONSTMSK and CONSTVAL features to techmap
 820      - Added _TECHMAP_CONNMAP_*_ feature to techmap
 821      - Added _TECHMAP_REPLACE_ feature to techmap
 822      - Added "connwrappers" command for wrap-extract-unwrap method
 823      - Added "extract -map %<design_name>" feature
 824      - Added "extract -ignore_param ..." and "extract -ignore_parameters"
 825      - Added "techmap -max_iter" option
 826
 827  * Improvements to "eval" and "sat" framework:
 828      - Now include a copy of Minisat (with build fixes applied)
 829      - Switched to Minisat::SimpSolver as SAT back-end
 830      - Added "sat -dump_vcd" feature
 831      - Added "sat -dump_cnf" feature
 832      - Added "sat -initsteps <N>" feature
 833      - Added "freduce -stop <N>" feature
 834      - Added "freduce -dump <prefix>" feature
 835
 836  * Integration with ABC:
 837      - Updated ABC rev to 7600ffb9340c
 838
 839  * Improvements in the internal APIs:
 840      - Added RTLIL::Module::add... helper methods
 841      - Various build fixes for OSX (Darwin) and OpenBSD
 842
 843
 844 Yosys 0.1.0 .. Yosys 0.2.0
 845 --------------------------
 846
 847  * Changes to the driver program:
 848      - Added "yosys -h" and "yosys -H"
 849      - Added support for backslash line continuation in scripts
 850      - Added support for #-comments in same line as command
 851      - Added "echo" and "log" commands
 852
 853  * Improvements in Verilog frontend:
 854      - Added support for local registers in named blocks
 855      - Added support for "case" in "generate" blocks
 856      - Added support for $clog2 system function
 857      - Added support for basic SystemVerilog assert statements
 858      - Added preprocessor support for macro arguments
 859      - Added preprocessor support for `elsif statement
 860      - Added "verilog_defaults" command
 861      - Added read_verilog -icells option
 862      - Added support for constant sizes from parameters
 863      - Added "read_verilog -setattr"
 864      - Added support for function returning 'integer'
 865      - Added limited support for function calls in parameter values
 866      - Added "read_verilog -defer" to suppress evaluation of modules with default parameters
 867
 868  * Other front- and back-ends:
 869      - Added BTOR backend
 870      - Added Liberty frontend
 871
 872  * Improvements in technology mapping:
 873      - The "dfflibmap" command now strongly prefers solutions with
 874            no inverters in clock paths
 875      - The "dfflibmap" command now prefers cells with smaller area
 876      - Added support for multiple -map options to techmap
 877      - Added "dfflibmap" support for //-comments in liberty files
 878      - Added "memory_unpack" command to revert "memory_collect"
 879      - Added standard techmap rule "techmap -share_map pmux2mux.v"
 880      - Added "iopadmap -bits"
 881      - Added "setundef" command
 882      - Added "hilomap" command
 883
 884  * Changes in the internal cell library:
 885      - Major rewrite of simlib.v for better compatibility with other tools
 886      - Added PRIORITY parameter to $memwr cells
 887      - Added TRANSPARENT parameter to $memrd cells
 888      - Added RD_TRANSPARENT parameter to $mem cells
 889      - Added $bu0 cell (always 0-extend, even undef MSB)
 890      - Added $assert cell type
 891      - Added $slice and $concat cell types
 892
 893  * Integration with ABC:
 894      - Updated ABC to hg rev 2058c8ccea68
 895      - Tighter integration of ABC build with Yosys build. The make
 896            targets 'make abc' and 'make install-abc' are now obsolete.
 897      - Added support for passing FFs from one clock domain through ABC
 898      - Now always use BLIF as exchange format with ABC
 899      - Added support for "abc -script +<command_sequence>"
 900      - Improved standard ABC recipe
 901      - Added support for "keep" attribute to abc command
 902      - Added "abc -dff / -clk / -keepff" options
 903
 904  * Improvements to "eval" and "sat" framework:
 905      - Added support for "0" and "~0" in right-hand side -set expressions
 906      - Added "eval -set-undef" and "eval -table"
 907      - Added "sat -set-init" and "sat -set-init-*" for sequential problems
 908      - Added undef support to SAT solver, incl. various new "sat" options
 909      - Added correct support for === and !== for "eval" and "sat"
 910      - Added "sat -tempinduct" (default -seq is now non-induction sequential)
 911      - Added "sat -prove-asserts"
 912      - Complete rewrite of the 'freduce' command
 913      - Added "miter" command
 914      - Added "sat -show-inputs" and "sat -show-outputs"
 915      - Added "sat -ignore_unknown_cells" (now produce an error by default)
 916      - Added "sat -falsify"
 917      - Now "sat -verify" and "sat -falsify" can also be used without "-prove"
 918      - Added "expose" command
 919      - Added support for @<sel_name> to sat and eval signal expressions
 920
 921  * Changes in the 'make test' framework and auxiliary test tools:
 922      - Added autotest.sh -p and -f options
 923      - Replaced autotest.sh ISIM support with XSIM support
 924      - Added test cases for SAT framework
 925
 926  * Added "abbreviated IDs":
 927      - Now $<something>$foo can be abbreviated as $foo.
 928      - Usually this last part is a unique id (from RTLIL::autoidx)
 929      - This abbreviated IDs are now also used in "show" output
 930
 931  * Other changes to selection framework:
 932      - Now */ is optional in */<mode>:<arg> expressions
 933      - Added "select -assert-none" and "select -assert-any"
 934      - Added support for matching modules by attribute (A:<expr>)
 935      - Added "select -none"
 936      - Added support for r:<expr> pattern for matching cell parameters
 937      - Added support for !=, <, <=, >=, > for attribute and parameter matching
 938      - Added support for %s for selecting sub-modules
 939      - Added support for %m for expanding selections to whole modules
 940      - Added support for i:*, o:* and x:* pattern for selecting module ports
 941      - Added support for s:<expr> pattern for matching wire width
 942      - Added support for %a operation to select wire aliases
 943
 944  * Various other changes to commands and options:
 945      - The "ls" command now supports wildcards
 946      - Added "show -pause" and "show -format dot"
 947      - Added "show -color" support for cells
 948      - Added "show -label" and "show -notitle"
 949      - Added "dump -m" and "dump -n"
 950      - Added "history" command
 951      - Added "rename -hide"
 952      - Added "connect" command
 953      - Added "splitnets -driver"
 954      - Added "opt_const -mux_undef"
 955      - Added "opt_const -mux_bool"
 956      - Added "opt_const -undriven"
 957      - Added "opt -mux_undef -mux_bool -undriven -purge"
 958      - Added "hierarchy -libdir"
 959      - Added "hierarchy -purge_lib" (by default now do not remove lib cells)
 960      - Added "delete" command
 961      - Added "dump -append"
 962      - Added "setattr" and "setparam" commands
 963      - Added "design -stash/-copy-from/-copy-to"
 964      - Added "copy" command
 965      - Added "splice" command
 966