CHANGELOG

   1
   2 List of major changes and improvements between releases
   3 =======================================================
   4
   5 Yosys 0.12 .. Yosys 0.12-dev
   6 --------------------------
   7
   8 Yosys 0.11 .. Yosys 0.12
   9 --------------------------
  10
  11  * Various
  12     - Added iopadmap native support for negative-polarity output enable
  13     - ABC update
  14
  15  * SystemVerilog
  16     - Support parameters using struct as a wiretype
  17     - Fixed regression preventing the use array querying functions in case
  18       expressions and case item expressions
  19     - Fixed static size casts inadvertently limiting the result width of binary
  20       operations
  21     - Fixed static size casts ignoring expression signedness
  22     - Fixed static size casts not extending unbased unsized literals
  23     - Added automatic `nosync` inference for local variables in `always_comb`
  24       procedures which are always assigned before they are used to avoid errant
  25       latch inference
  26
  27  * New commands and options
  28     - Added "-genlib" option to "abc" pass
  29     - Added "sta" very crude static timing analysis pass
  30
  31  * Verific support
  32     - Fixed memory block size in import
  33
  34  * New back-ends
  35     - Added support for GateMate FPGA from Cologne Chip AG
  36
  37  * Intel ALM support
  38     - Added preliminary Arria V support
  39
  40
  41 Yosys 0.10 .. Yosys 0.11
  42 --------------------------
  43
  44  * Various
  45     - Added $aldff and $aldffe (flip-flops with async load) cells
  46
  47  * SystemVerilog
  48     - Fixed an issue which prevented writing directly to a memory word via a
  49       connection to an output port
  50     - Fixed an issue which prevented unbased unsized literals (e.g., `'1`) from
  51       filling the width of a cell input
  52     - Fixed an issue where connecting a slice covering the entirety of a signed
  53       signal to a cell input would cause a failed assertion
  54
  55  * Verific support
  56     - Importer support for {PRIM,WIDE_OPER}_DFF
  57     - Importer support for PRIM_BUFIF1
  58     - Option to use Verific without VHDL support
  59     - Importer support for {PRIM,WIDE_OPER}_DLATCH{,RS}
  60     - Added -cfg option for getting/setting Verific runtime flags
  61
  62 Yosys 0.9 .. Yosys 0.10
  63 --------------------------
  64
  65  * Various
  66     - Added automatic gzip decompression for frontends
  67     - Added $_NMUX_ cell type
  68     - Added automatic gzip compression (based on filename extension) for backends
  69     - Improve attribute and parameter encoding in JSON to avoid ambiguities between
  70       bit vectors and strings containing [01xz]*
  71     - Improvements in pmgen: subpattern and recursive matches
  72     - Support explicit FIRRTL properties
  73     - Improvements in pmgen: slices, choices, define, generate
  74     - Added "_TECHMAP_WIREINIT_*_" parameter and "_TECHMAP_REMOVEINIT_*_" wire for "techmap" pass
  75     - Added +/mul2dsp.v for decomposing wide multipliers to custom-sized ones
  76     - Added new frontend: rpc
  77     - Added --version and -version as aliases for -V
  78     - Improve yosys-smtbmc "solver not found" handling
  79     - Improved support of $readmem[hb] Memory Content File inclusion
  80     - Added CXXRTL backend
  81     - Use YosysHQ/abc instead of upstream berkeley-abc/abc
  82     - Added WASI platform support.
  83     - Added extmodule support to firrtl backend
  84     - Added $divfloor and $modfloor cells
  85     - Added $adffe, $dffsre, $sdff, $sdffe, $sdffce, $adlatch cells
  86     - Added "_TECHMAP_CELLNAME_" parameter for "techmap" pass
  87     - Added firrtl backend support for generic parameters in blackbox components
  88     - Added $meminit_v2 cells (with support for write mask)
  89     - Added $mem_v2, $memrd_v2, $memwr_v2, with the following features:
  90       - write priority masks, per write/write port pair
  91       - transparency and undefined collision behavior masks, per read/write port pair
  92       - read port reset and initialization
  93       - wide ports (accessing a naturally aligned power-of-two number of memory cells)
  94
  95  * New commands and options
  96     - Added "write_xaiger" backend
  97     - Added "read_xaiger"
  98     - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only)
  99     - Added "synth -abc9" (experimental)
 100     - Added "script -scriptwire"
 101     - Added "clkbufmap" pass
 102     - Added "extractinv" pass and "invertible_pin" attribute
 103     - Added "proc_clean -quiet"
 104     - Added "proc_prune" pass
 105     - Added "stat -tech cmos"
 106     - Added "opt_share" pass, run as part of "opt -full"
 107     - Added "-match-init" option to "dff2dffs" pass
 108     - Added "equiv_opt -multiclock"
 109     - Added "techmap_autopurge" support to techmap
 110     - Added "add -mod <modname[s]>"
 111     - Added "paramap" pass
 112     - Added "portlist" command
 113     - Added "check -mapped"
 114     - Added "check -allow-tbuf"
 115     - Added "autoname" pass
 116     - Added "write_verilog -extmem"
 117     - Added "opt_mem" pass
 118     - Added "scratchpad" pass
 119     - Added "fminit" pass
 120     - Added "opt_lut_ins" pass
 121     - Added "logger" pass
 122     - Added "show -nobg"
 123     - Added "exec" command
 124     - Added "design -delete"
 125     - Added "design -push-copy"
 126     - Added "qbfsat" command
 127     - Added "select -unset"
 128     - Added "dfflegalize" pass
 129     - Removed "opt_expr -clkinv" option, made it the default
 130     - Added "proc -nomux
 131     - Merged "dffsr2dff", "opt_rmdff", "dff2dffe", "dff2dffs", "peepopt.dffmux" passes into a new "opt_dff" pass
 132
 133  * SystemVerilog
 134     - Added checking of always block types (always_comb, always_latch and always_ff)
 135     - Added support for wildcard port connections (.*)
 136     - Added support for enum typedefs
 137     - Added support for structs and packed unions.
 138     - Allow constant function calls in for loops and generate if and case
 139     - Added support for static cast
 140     - Added support for logic typed parameters
 141     - Fixed generate scoping issues
 142     - Added support for real-valued parameters
 143     - Allow localparams in constant functions
 144     - Module name scope support
 145     - Support recursive functions using ternary expressions
 146     - Extended support for integer types
 147     - Support for parameters without default values
 148     - Allow globals in one file to depend on globals in another
 149     - Added support for: *=, /=, %=, <<=, >>=, <<<=, >>>=
 150     - Added support for parsing the 'bind' construct
 151     - support declaration in procedural for initialization
 152     - support declaration in generate for initialization
 153     - Support wand and wor of data types
 154
 155  * Verific support
 156     - Added "verific -L"
 157     - Add Verific SVA support for "always" properties
 158     - Add Verific support for SVA nexttime properties
 159     - Improve handling of verific primitives in "verific -import -V" mode
 160     - Import attributes for wires
 161     - Support VHDL enums
 162     - Added support for command files
 163
 164  * New back-ends
 165     - Added initial EFINIX support
 166     - Added Intel ALM: alternative synthesis for Intel FPGAs
 167     - Added initial Nexus support
 168     - Added initial MachXO2 support
 169     - Added initial QuickLogic PolarPro 3 support
 170
 171  * ECP5 support
 172     - Renamed labels/options in synth_ecp5 (e.g. dram -> map_lutram; -nodram -> -nolutram)
 173     - Added "synth_ecp5 -abc9" (experimental)
 174     - Added "synth_ecp5 -nowidelut"
 175     - "synth_ecp5" to now infer DSP blocks (-nodsp to disable, experimental)
 176
 177  * iCE40 support
 178     - Added "synth_ice40 -abc9" (experimental)
 179     - Added "synth_ice40 -device"
 180     - Renamed labels/options in synth_ice40 (e.g. dram -> map_lutram; -nodram -> -nolutram)
 181     - Added "ice40_wrapcarry" to encapsulate SB_LUT+SB_CARRY pairs for techmapping
 182     - Removed "ice40_unlut"
 183     - Added "ice40_dsp" for Lattice iCE40 DSP packing
 184     - "synth_ice40 -dsp" to infer DSP blocks
 185
 186  * Xilinx support
 187     - Added "synth_xilinx -abc9" (experimental)
 188     - Added "synth_xilinx -nocarry"
 189     - Added "synth_xilinx -nowidelut"
 190     - "synth_xilinx" to now infer wide multiplexers (-widemux <min> to enable)
 191     - Renamed labels/options in synth_xilinx (e.g. dram -> map_lutram; -nodram -> -nolutram)
 192     - Added "synth_xilinx -family xc6s" for Spartan 6 support (experimental)
 193     - Added "synth_xilinx -ise" (experimental)
 194     - Added "synth_xilinx -iopad"
 195     - "synth_xilinx" now automatically inserts clock buffers (add -noclkbuf to disable)
 196     - Added "xilinx_srl" for Xilinx shift register extraction
 197     - Removed "shregmap -tech xilinx" (superseded by "xilinx_srl")
 198     - Added "xilinx_dsp" for Xilinx DSP packing
 199     - "synth_xilinx" to now infer DSP blocks (-nodsp to disable)
 200     - Added latch support to synth_xilinx
 201     - Added support for flip-flops with synchronous reset to synth_xilinx
 202     - Added support for flip-flops with reset and enable to synth_xilinx
 203     - Added "xilinx_dffopt" pass
 204     - Added "synth_xilinx -dff"
 205
 206  * Intel support
 207     - Renamed labels in synth_intel (e.g. bram -> map_bram)
 208     - synth_intel: cyclone10 -> cyclone10lp, a10gx -> arria10gx
 209     - Added "intel_alm -abc9" (experimental)
 210
 211  * CoolRunner2 support
 212     - Separate and improve buffer cell insertion pass
 213     - Use extract_counter to optimize counters
 214
 215 Yosys 0.8 .. Yosys 0.9
 216 ----------------------
 217
 218  * Various
 219     - Many bugfixes and small improvements
 220     - Added support for SystemVerilog interfaces and modports
 221     - Added "write_edif -attrprop"
 222     - Added "opt_lut" pass
 223     - Added "gate2lut.v" techmap rule
 224     - Added "rename -src"
 225     - Added "equiv_opt" pass
 226     - Added "flowmap" LUT mapping pass
 227     - Added "rename -wire" to rename cells based on the wires they drive
 228     - Added "bugpoint" for creating minimised testcases
 229     - Added "write_edif -gndvccy"
 230     - "write_verilog" to escape Verilog keywords
 231     - Fixed sign handling of real constants
 232     - "write_verilog" to write initial statement for initial flop state
 233     - Added pmgen pattern matcher generator
 234     - Fixed opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_
 235     - Added "setundef -params" to replace undefined cell parameters
 236     - Renamed "yosys -D" to "yosys -U", added "yosys -D" to set Verilog defines
 237     - Fixed handling of defparam when default_nettype is none
 238     - Fixed "wreduce" flipflop handling
 239     - Fixed FIRRTL to Verilog process instance subfield assignment
 240     - Added "write_verilog -siminit"
 241     - Several fixes and improvements for mem2reg memories
 242     - Fixed handling of task output ports in clocked always blocks
 243     - Improved handling of and-with-1 and or-with-0 in "opt_expr"
 244     - Added "read_aiger" frontend
 245     - Added "mutate" pass
 246     - Added "hdlname" attribute
 247     - Added "rename -output"
 248     - Added "read_ilang -lib"
 249     - Improved "proc" full_case detection and handling
 250     - Added "whitebox" and "lib_whitebox" attributes
 251     - Added "read_verilog -nowb", "flatten -wb" and "wbflip"
 252     - Added Python bindings and support for Python plug-ins
 253     - Added "pmux2shiftx"
 254     - Added log_debug framework for reduced default verbosity
 255     - Improved "opt_expr" and "opt_clean" handling of (partially) undriven and/or unused wires
 256     - Added "peepopt" peephole optimisation pass using pmgen
 257     - Added approximate support for SystemVerilog "var" keyword
 258     - Added parsing of "specify" blocks into $specrule and $specify[23]
 259     - Added support for attributes on parameters and localparams
 260     - Added support for parsing attributes on port connections
 261     - Added "wreduce -keepdc"
 262     - Added support for optimising $dffe and $_DFFE_* cells in "opt_rmdff"
 263     - Added Verilog wand/wor wire type support
 264     - Added support for elaboration system tasks
 265     - Added "muxcover -mux{4,8,16}=<cost>"
 266     - Added "muxcover -dmux=<cost>"
 267     - Added "muxcover -nopartial"
 268     - Added "muxpack" pass
 269     - Added "pmux2shiftx -norange"
 270     - Added support for "~" in filename parsing
 271     - Added "read_verilog -pwires" feature to turn parameters into wires
 272     - Fixed sign extension of unsized constants with 'bx and 'bz MSB
 273     - Fixed genvar to be a signed type
 274     - Added support for attributes on case rules
 275     - Added "upto" and "offset" to JSON frontend and backend
 276     - Several liberty file parser improvements
 277     - Fixed handling of more complex BRAM patterns
 278     - Add "write_aiger -I -O -B"
 279
 280  * Formal Verification
 281     - Added $changed support to read_verilog
 282     - Added "read_verilog -noassert -noassume -assert-assumes"
 283     - Added btor ops for $mul, $div, $mod and $concat
 284     - Added yosys-smtbmc support for btor witnesses
 285     - Added "supercover" pass
 286     - Fixed $global_clock handling vs autowire
 287     - Added $dffsr support to "async2sync"
 288     - Added "fmcombine" pass
 289     - Added memory init support in "write_btor"
 290     - Added "cutpoint" pass
 291     - Changed "ne" to "neq" in btor2 output
 292     - Added support for SVA "final" keyword
 293     - Added "fmcombine -initeq -anyeq"
 294     - Added timescale and generated-by header to yosys-smtbmc vcd output
 295     - Improved BTOR2 handling of undriven wires
 296
 297  * Verific support
 298     - Enabled Verific flags vhdl_support_variable_slice and veri_elaborate_top_level_modules_having_interface_ports
 299     - Improved support for asymmetric memories
 300     - Added "verific -chparam"
 301     - Fixed "verific -extnets" for more complex situations
 302     - Added "read -verific" and "read -noverific"
 303     - Added "hierarchy -chparam"
 304
 305  * New back-ends
 306     - Added initial Anlogic support
 307     - Added initial SmartFusion2 and IGLOO2 support
 308
 309  * ECP5 support
 310     - Added "synth_ecp5 -nowidelut"
 311     - Added BRAM inference support to "synth_ecp5"
 312     - Added support for transforming Diamond IO and flipflop primitives
 313
 314  * iCE40 support
 315     - Added "ice40_unlut" pass
 316     - Added "synth_ice40 -relut"
 317     - Added "synth_ice40 -noabc"
 318     - Added "synth_ice40 -dffe_min_ce_use"
 319     - Added DSP inference support using pmgen
 320     - Added support for initialising BRAM primitives from a file
 321     - Added iCE40 Ultra RGB LED driver cells
 322
 323  * Xilinx support
 324     - Use "write_edif -pvector bra" for Xilinx EDIF files
 325     - Fixes for VPR place and route support with "synth_xilinx"
 326     - Added more cell simulation models
 327     - Added "synth_xilinx -family"
 328     - Added "stat -tech xilinx" to estimate logic cell usage
 329     - Added "synth_xilinx -nocarry"
 330     - Added "synth_xilinx -nowidelut"
 331     - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
 332     - Added support for mapping RAM32X1D
 333
 334 Yosys 0.7 .. Yosys 0.8
 335 ----------------------
 336
 337  * Various
 338     - Many bugfixes and small improvements
 339     - Strip debug symbols from installed binary
 340     - Replace -ignore_redef with -[no]overwrite in front-ends
 341     - Added write_verilog hex dump support, add -nohex option
 342     - Added "write_verilog -decimal"
 343     - Added "scc -set_attr"
 344     - Added "verilog_defines" command
 345     - Remember defines from one read_verilog to next
 346     - Added support for hierarchical defparam
 347     - Added FIRRTL back-end
 348     - Improved ABC default scripts
 349     - Added "design -reset-vlog"
 350     - Added "yosys -W regex", "yosys -w regex", and "yosys -e regex"
 351     - Added Verilog $rtoi and $itor support
 352     - Added "check -initdrv"
 353     - Added "read_blif -wideports"
 354     - Added support for SystemVerilog "++" and "--" operators
 355     - Added support for SystemVerilog unique, unique0, and priority case
 356     - Added "write_edif" options for edif "flavors"
 357     - Added support for resetall compiler directive
 358     - Added simple C beck-end (bitwise combinatorical only atm)
 359     - Added $_ANDNOT_ and $_ORNOT_ cell types
 360     - Added cell library aliases to "abc -g"
 361     - Added "setundef -anyseq"
 362     - Added "chtype" command
 363     - Added "design -import"
 364     - Added "write_table" command
 365     - Added "read_json" command
 366     - Added "sim" command
 367     - Added "extract_fa" and "extract_reduce" commands
 368     - Added "extract_counter" command
 369     - Added "opt_demorgan" command
 370     - Added support for $size and $bits SystemVerilog functions
 371     - Added "blackbox" command
 372     - Added "ltp" command
 373     - Added support for editline as replacement for readline
 374     - Added warnings for driver-driver conflicts between FFs (and other cells) and constants
 375     - Added "yosys -E" for creating Makefile dependencies files
 376     - Added "synth -noshare"
 377     - Added "memory_nordff"
 378     - Added "setundef -undef -expose -anyconst"
 379     - Added "expose -input"
 380     - Added specify/specparam parser support (simply ignore them)
 381     - Added "write_blif -inames -iattr"
 382     - Added "hierarchy -simcheck"
 383     - Added an option to statically link abc into yosys
 384     - Added protobuf back-end
 385     - Added BLIF parsing support for .conn and .cname
 386     - Added read_verilog error checking for reg/wire/logic misuse
 387     - Added "make coverage" and ENABLE_GCOV build option
 388
 389  * Changes in Yosys APIs
 390     - Added ConstEval defaultval feature
 391     - Added {get,set}_src_attribute() methods on RTLIL::AttrObject
 392     - Added SigSpec::is_fully_ones() and Const::is_fully_ones()
 393     - Added log_file_warning() and log_file_error() functions
 394
 395  * Formal Verification
 396     - Added "write_aiger"
 397     - Added "yosys-smtbmc --aig"
 398     - Added "always <positive_int>" to .smtc format
 399     - Added $cover cell type and support for cover properties
 400     - Added $fair/$live cell type and support for liveness properties
 401     - Added smtbmc support for memory vcd dumping
 402     - Added "chformal" command
 403     - Added "write_smt2 -stbv" and "write_smt2 -stdt"
 404     - Fix equiv_simple, old behavior now available with "equiv_simple -short"
 405     - Change to Yices2 as default SMT solver (it is GPL now)
 406     - Added "yosys-smtbmc --presat" (now default in SymbiYosys)
 407     - Added "yosys-smtbmc --smtc-init --smtc-top --noinit"
 408     - Added a brand new "write_btor" command for BTOR2
 409     - Added clk2fflogic memory support and other improvements
 410     - Added "async memory write" support to write_smt2
 411     - Simulate clock toggling in yosys-smtbmc VCD output
 412     - Added $allseq/$allconst cells for EA-solving
 413     - Make -nordff the default in "prep"
 414     - Added (* gclk *) attribute
 415     - Added "async2sync" pass for single-clock designs with async resets
 416
 417  * Verific support
 418     - Many improvements in Verific front-end
 419     - Added proper handling of concurent SVA properties
 420     - Map "const" and "rand const" to $anyseq/$anyconst
 421     - Added "verific -import -flatten" and "verific -import -extnets"
 422     - Added "verific -vlog-incdir -vlog-define -vlog-libdir"
 423     - Remove PSL support (because PSL has been removed in upstream Verific)
 424     - Improve integration with "hierarchy" command design elaboration
 425     - Added YOSYS_NOVERIFIC for running non-verific test cases with verific bin
 426     - Added simpilied "read" command that automatically uses verific if available
 427     - Added "verific -set-<severity> <msg_id>.."
 428     - Added "verific -work <libname>"
 429
 430  * New back-ends
 431     - Added initial Coolrunner-II support
 432     - Added initial eASIC support
 433     - Added initial ECP5 support
 434
 435  * GreenPAK Support
 436     - Added support for GP_DLATCH, GP_SPI, GP_DCMx, GP_COUNTx, etc.
 437
 438  * iCE40 Support
 439     - Add "synth_ice40 -vpr"
 440     - Add "synth_ice40 -nodffe"
 441     - Add "synth_ice40 -json"
 442     - Add Support for UltraPlus cells
 443
 444  * MAX10 and Cyclone IV Support
 445     - Added initial version of metacommand "synth_intel".
 446     - Improved write_verilog command to produce VQM netlist for Quartus Prime.
 447     - Added support for MAX10 FPGA family synthesis.
 448     - Added support for Cyclone IV family synthesis.
 449     - Added example of implementation for DE2i-150 board.
 450     - Added example of implementation for MAX10 development kit.
 451     - Added LFSR example from Asic World.
 452     - Added "dffinit -highlow" for mapping to Intel primitives
 453
 454
 455 Yosys 0.6 .. Yosys 0.7
 456 ----------------------
 457
 458  * Various
 459     - Added "yosys -D" feature
 460     - Added support for installed plugins in $(DATDIR)/plugins/
 461     - Renamed opt_const to opt_expr
 462     - Renamed opt_share to opt_merge
 463     - Added "prep -flatten" and "synth -flatten"
 464     - Added "prep -auto-top" and "synth -auto-top"
 465     - Using "mfs" and "lutpack" in ABC lut mapping
 466     - Support for abstract modules in chparam
 467     - Cleanup abstract modules at end of "hierarchy -top"
 468     - Added tristate buffer support to iopadmap
 469     - Added opt_expr support for div/mod by power-of-two
 470     - Added "select -assert-min <N> -assert-max <N>"
 471     - Added "attrmvcp" pass
 472     - Added "attrmap" command
 473     - Added "tee +INT -INT"
 474     - Added "zinit" pass
 475     - Added "setparam -type"
 476     - Added "shregmap" pass
 477     - Added "setundef -init"
 478     - Added "nlutmap -assert"
 479     - Added $sop cell type and "abc -sop -I <num> -P <num>"
 480     - Added "dc2" to default ABC scripts
 481     - Added "deminout"
 482     - Added "insbuf" command
 483     - Added "prep -nomem"
 484     - Added "opt_rmdff -keepdc"
 485     - Added "prep -nokeepdc"
 486     - Added initial version of "synth_gowin"
 487     - Added "fsm_expand -full"
 488     - Added support for fsm_encoding="user"
 489     - Many improvements in GreenPAK4 support
 490     - Added black box modules for all Xilinx 7-series lib cells
 491     - Added synth_ice40 support for latches via logic loops
 492     - Fixed ice40_opt lut unmapping, added "ice40_opt -unlut"
 493
 494  * Build System
 495     - Added ABCEXTERNAL and ABCURL make variables
 496     - Added BINDIR, LIBDIR, and DATDIR make variables
 497     - Added PKG_CONFIG make variable
 498     - Added SEED make variable (for "make test")
 499     - Added YOSYS_VER_STR make variable
 500     - Updated min GCC requirement to GCC 4.8
 501     - Updated required Bison version to Bison 3.x
 502
 503  * Internal APIs
 504     - Added ast.h to exported headers
 505     - Added ScriptPass helper class for script-like passes
 506     - Added CellEdgesDatabase API
 507
 508  * Front-ends and Back-ends
 509     - Added filename glob support to all front-ends
 510     - Added avail (black-box) module params to ilang format
 511     - Added $display %m support
 512     - Added support for $stop Verilog system task
 513     - Added support for SystemVerilog packages
 514     - Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b}
 515     - Added support for "active high" and "active low" latches in read_blif and write_blif
 516     - Use init value "2" for all uninitialized FFs in BLIF back-end
 517     - Added "read_blif -sop"
 518     - Added "write_blif -noalias"
 519     - Added various write_blif options for VTR support
 520     - write_json: also write module attributes.
 521     - Added "write_verilog -nodec -nostr -defparam"
 522     - Added "read_verilog -norestrict -assume-asserts"
 523     - Added support for bus interfaces to "read_liberty -lib"
 524     - Added liberty parser support for types within cell decls
 525     - Added "write_verilog -renameprefix -v"
 526     - Added "write_edif -nogndvcc"
 527
 528  * Formal Verification
 529     - Support for hierarchical designs in smt2 back-end
 530     - Yosys-smtbmc: Support for hierarchical VCD dumping
 531     - Added $initstate cell type and vlog function
 532     - Added $anyconst and $anyseq cell types and vlog functions
 533     - Added printing of code loc of failed asserts to yosys-smtbmc
 534     - Added memory_memx pass, "memory -memx", and "prep -memx"
 535     - Added "proc_mux -ifx"
 536     - Added "yosys-smtbmc -g"
 537     - Deprecated "write_smt2 -regs" (by default on now)
 538     - Made "write_smt2 -bv -mem" default, added "write_smt2 -nobv -nomem"
 539     - Added support for memories to smtio.py
 540     - Added "yosys-smtbmc --dump-vlogtb"
 541     - Added "yosys-smtbmc --smtc --dump-smtc"
 542     - Added "yosys-smtbmc --dump-all"
 543     - Added assertpmux command
 544     - Added "yosys-smtbmc --unroll"
 545     - Added $past, $stable, $rose, $fell SVA functions
 546     - Added "yosys-smtbmc --noinfo and --dummy"
 547     - Added "yosys-smtbmc --noincr"
 548     - Added "yosys-smtbmc --cex <filename>"
 549     - Added $ff and $_FF_ cell types
 550     - Added $global_clock verilog syntax support for creating $ff cells
 551     - Added clk2fflogic
 552
 553
 554 Yosys 0.5 .. Yosys 0.6
 555 ----------------------
 556
 557  * Various
 558      - Added Contributor Covenant Code of Conduct
 559      - Various improvements in dict<> and pool<>
 560      - Added hashlib::mfp and refactored SigMap
 561      - Improved support for reals as module parameters
 562      - Various improvements in SMT2 back-end
 563      - Added "keep_hierarchy" attribute
 564      - Verilog front-end: define `BLACKBOX in -lib mode
 565      - Added API for converting internal cells to AIGs
 566      - Added ENABLE_LIBYOSYS Makefile option
 567      - Removed "techmap -share_map" (use "-map +/filename" instead)
 568      - Switched all Python scripts to Python 3
 569      - Added support for $display()/$write() and $finish() to Verilog front-end
 570      - Added "yosys-smtbmc" formal verification flow
 571      - Added options for clang sanitizers to Makefile
 572
 573  * New commands and options
 574      - Added "scc -expect <N> -nofeedback"
 575      - Added "proc_dlatch"
 576      - Added "check"
 577      - Added "select %xe %cie %coe %M %C %R"
 578      - Added "sat -dump_json" (WaveJSON format)
 579      - Added "sat -tempinduct-baseonly -tempinduct-inductonly"
 580      - Added "sat -stepsize" and "sat -tempinduct-step"
 581      - Added "sat -show-regs -show-public -show-all"
 582      - Added "write_json" (Native Yosys JSON format)
 583      - Added "write_blif -attr"
 584      - Added "dffinit"
 585      - Added "chparam"
 586      - Added "muxcover"
 587      - Added "pmuxtree"
 588      - Added memory_bram "make_outreg" feature
 589      - Added "splice -wires"
 590      - Added "dff2dffe -direct-match"
 591      - Added simplemap $lut support
 592      - Added "read_blif"
 593      - Added "opt_share -share_all"
 594      - Added "aigmap"
 595      - Added "write_smt2 -mem -regs -wires"
 596      - Added "memory -nordff"
 597      - Added "write_smv"
 598      - Added "synth -nordff -noalumacc"
 599      - Added "rename -top new_name"
 600      - Added "opt_const -clkinv"
 601      - Added "synth -nofsm"
 602      - Added "miter -assert"
 603      - Added "read_verilog -noautowire"
 604      - Added "read_verilog -nodpi"
 605      - Added "tribuf"
 606      - Added "lut2mux"
 607      - Added "nlutmap"
 608      - Added "qwp"
 609      - Added "test_cell -noeval"
 610      - Added "edgetypes"
 611      - Added "equiv_struct"
 612      - Added "equiv_purge"
 613      - Added "equiv_mark"
 614      - Added "equiv_add -try -cell"
 615      - Added "singleton"
 616      - Added "abc -g -luts"
 617      - Added "torder"
 618      - Added "write_blif -cname"
 619      - Added "submod -copy"
 620      - Added "dffsr2dff"
 621      - Added "stat -liberty"
 622
 623  * Synthesis metacommands
 624      - Various improvements in synth_xilinx
 625      - Added synth_ice40 and synth_greenpak4
 626      - Added "prep" metacommand for "synthesis lite"
 627
 628  * Cell library changes
 629      - Added cell types to "help" system
 630      - Added $meminit cell type
 631      - Added $assume cell type
 632      - Added $_MUX4_, $_MUX8_, and $_MUX16_ cells
 633      - Added $tribuf and $_TBUF_ cell types
 634      - Added read-enable to memory model
 635
 636  * YosysJS
 637      - Various improvements in emscripten build
 638      - Added alternative webworker-based JS API
 639      - Added a few example applications
 640
 641
 642 Yosys 0.4 .. Yosys 0.5
 643 ----------------------
 644
 645  * API changes
 646      - Added log_warning()
 647      - Added eval_select_args() and eval_select_op()
 648      - Added cell->known(), cell->input(portname), cell->output(portname)
 649      - Skip blackbox modules in design->selected_modules()
 650      - Replaced std::map<> and std::set<> with dict<> and pool<>
 651      - New SigSpec::extend() is what used to be SigSpec::extend_u0()
 652      - Added YS_OVERRIDE, YS_FINAL, YS_ATTRIBUTE, YS_NORETURN
 653
 654  * Cell library changes
 655      - Added flip-flops with enable ($dffe etc.)
 656      - Added $equiv cells for equivalence checking framework
 657
 658  * Various
 659      - Updated ABC to hg rev 61ad5f908c03
 660      - Added clock domain partitioning to ABC pass
 661      - Improved plugin building (see "yosys-config --build")
 662      - Added ENABLE_NDEBUG Makefile flag for high-performance builds
 663      - Added "yosys -d", "yosys -L" and other driver improvements
 664      - Added support for multi-bit (array) cell ports to "write_edif"
 665      - Now printing most output to stdout, not stderr
 666      - Added "onehot" attribute (set by "fsm_map")
 667      - Various performance improvements
 668      - Vastly improved Xilinx flow
 669      - Added "make unsintall"
 670
 671  * Equivalence checking
 672      - Added equivalence checking commands:
 673          equiv_make equiv_simple equiv_status
 674          equiv_induct equiv_miter
 675          equiv_add equiv_remove
 676
 677  * Block RAM support:
 678      - Added "memory_bram" command
 679      - Added BRAM support to Xilinx flow
 680
 681  * Other New Commands and Options
 682      - Added "dff2dffe"
 683      - Added "fsm -encfile"
 684      - Added "dfflibmap -prepare"
 685      - Added "write_blid -unbuf -undef -blackbox"
 686      - Added "write_smt2" for writing SMT-LIBv2 files
 687      - Added "test_cell -w -muxdiv"
 688      - Added "select -read"
 689
 690
 691 Yosys 0.3.0 .. Yosys 0.4
 692 ------------------------
 693
 694  * Platform Support
 695      - Added support for mxe-based cross-builds for win32
 696      - Added sourcecode-export as VisualStudio project
 697      - Added experimental EMCC (JavaScript) support
 698
 699  * Verilog Frontend
 700      - Added -sv option for SystemVerilog (and automatic *.sv file support)
 701      - Added support for real-valued constants and constant expressions
 702      - Added support for non-standard "via_celltype" attribute on task/func
 703      - Added support for non-standard "module mod_name(...);" syntax
 704      - Added support for non-standard """ macro bodies
 705      - Added support for array with more than one dimension
 706      - Added support for $readmemh and $readmemb
 707      - Added support for DPI functions
 708
 709  * Changes in internal cell library
 710      - Added $shift and $shiftx cell types
 711      - Added $alu, $lcu, $fa and $macc cell types
 712      - Removed $bu0 and $safe_pmux cell types
 713      - $mem/$memwr WR_EN input is now a per-data-bit enable signal
 714      - Added $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
 715      - Renamed ports of $lut cells (from I->O to A->Y)
 716      - Renamed $_INV_ to $_NOT_
 717
 718  * Changes for simple synthesis flows
 719      - There is now a "synth" command with a recommended default script
 720      - Many improvements in synthesis of arithmetic functions to gates
 721          - Multipliers and adders with many operands are using carry-save adder trees
 722          - Remaining adders are now implemented using Brent-Kung carry look-ahead adders
 723      - Various new high-level optimizations on RTL netlist
 724      - Various improvements in FSM optimization
 725      - Updated ABC to hg 5b5af75f1dda (from 2014-11-07)
 726
 727  * Changes in internal APIs and RTLIL
 728      - Added log_id() and log_cell() helper functions
 729      - Added function-like cell creation helpers
 730      - Added GetSize() function (like .size() but with int)
 731      - Major refactoring of RTLIL::Module and related classes
 732      - Major refactoring of RTLIL::SigSpec and related classes
 733      - Now RTLIL::IdString is essentially an int
 734      - Added macros for code coverage counters
 735      - Added some Makefile magic for pretty make logs
 736      - Added "kernel/yosys.h" with all the core definitions
 737      - Changed a lot of code from FILE* to c++ streams
 738      - Added RTLIL::Monitor API and "trace" command
 739      - Added "Yosys" C++ namespace
 740
 741  * Changes relevant to SAT solving
 742      - Added ezSAT::keep_cnf() and ezSAT::non_incremental()
 743      - Added native ezSAT support for vector shift ops
 744      - Updated MiniSAT to git 37dc6c67e2 (from 2013-09-25)
 745
 746  * New commands (or large improvements to commands)
 747      - Added "synth" command with default script
 748      - Added "share" (finally some real resource sharing)
 749      - Added "memory_share" (reduce number of ports on memories)
 750      - Added "wreduce" and "alumacc" commands
 751      - Added "opt -keepdc -fine -full -fast"
 752      - Added some "test_*" commands
 753
 754  * Various other changes
 755      - Added %D and %c select operators
 756      - Added support for labels in yosys scripts
 757      - Added support for here-documents in yosys scripts
 758      - Support "+/" prefix for files from proc_share_dir
 759      - Added "autoidx" statement to ilang language
 760      - Switched from "yosys-svgviewer" to "xdot"
 761      - Renamed "stdcells.v" to "techmap.v"
 762      - Various bug fixes and small improvements
 763      - Improved welcome and bye messages
 764
 765
 766 Yosys 0.2.0 .. Yosys 0.3.0
 767 --------------------------
 768
 769  * Driver program and overall behavior:
 770      - Added "design -push" and "design -pop"
 771      - Added "tee" command for redirecting log output
 772
 773  * Changes in the internal cell library:
 774      - Added $dlatchsr and $_DLATCHSR_???_ cell types
 775
 776  * Improvements in Verilog frontend:
 777      - Improved support for const functions (case, always, repeat)
 778      - The generate..endgenerate keywords are now optional
 779      - Added support for arrays of module instances
 780      - Added support for "`default_nettype" directive
 781      - Added support for "`line" directive
 782
 783  * Other front- and back-ends:
 784      - Various changes to "write_blif" options
 785      - Various improvements in EDIF backend
 786      - Added "vhdl2verilog" pseudo-front-end
 787      - Added "verific" pseudo-front-end
 788
 789  * Improvements in technology mapping:
 790      - Added support for recursive techmap
 791      - Added CONSTMSK and CONSTVAL features to techmap
 792      - Added _TECHMAP_CONNMAP_*_ feature to techmap
 793      - Added _TECHMAP_REPLACE_ feature to techmap
 794      - Added "connwrappers" command for wrap-extract-unwrap method
 795      - Added "extract -map %<design_name>" feature
 796      - Added "extract -ignore_param ..." and "extract -ignore_parameters"
 797      - Added "techmap -max_iter" option
 798
 799  * Improvements to "eval" and "sat" framework:
 800      - Now include a copy of Minisat (with build fixes applied)
 801      - Switched to Minisat::SimpSolver as SAT back-end
 802      - Added "sat -dump_vcd" feature
 803      - Added "sat -dump_cnf" feature
 804      - Added "sat -initsteps <N>" feature
 805      - Added "freduce -stop <N>" feature
 806      - Added "freduce -dump <prefix>" feature
 807
 808  * Integration with ABC:
 809      - Updated ABC rev to 7600ffb9340c
 810
 811  * Improvements in the internal APIs:
 812      - Added RTLIL::Module::add... helper methods
 813      - Various build fixes for OSX (Darwin) and OpenBSD
 814
 815
 816 Yosys 0.1.0 .. Yosys 0.2.0
 817 --------------------------
 818
 819  * Changes to the driver program:
 820      - Added "yosys -h" and "yosys -H"
 821      - Added support for backslash line continuation in scripts
 822      - Added support for #-comments in same line as command
 823      - Added "echo" and "log" commands
 824
 825  * Improvements in Verilog frontend:
 826      - Added support for local registers in named blocks
 827      - Added support for "case" in "generate" blocks
 828      - Added support for $clog2 system function
 829      - Added support for basic SystemVerilog assert statements
 830      - Added preprocessor support for macro arguments
 831      - Added preprocessor support for `elsif statement
 832      - Added "verilog_defaults" command
 833      - Added read_verilog -icells option
 834      - Added support for constant sizes from parameters
 835      - Added "read_verilog -setattr"
 836      - Added support for function returning 'integer'
 837      - Added limited support for function calls in parameter values
 838      - Added "read_verilog -defer" to suppress evaluation of modules with default parameters
 839
 840  * Other front- and back-ends:
 841      - Added BTOR backend
 842      - Added Liberty frontend
 843
 844  * Improvements in technology mapping:
 845      - The "dfflibmap" command now strongly prefers solutions with
 846            no inverters in clock paths
 847      - The "dfflibmap" command now prefers cells with smaller area
 848      - Added support for multiple -map options to techmap
 849      - Added "dfflibmap" support for //-comments in liberty files
 850      - Added "memory_unpack" command to revert "memory_collect"
 851      - Added standard techmap rule "techmap -share_map pmux2mux.v"
 852      - Added "iopadmap -bits"
 853      - Added "setundef" command
 854      - Added "hilomap" command
 855
 856  * Changes in the internal cell library:
 857      - Major rewrite of simlib.v for better compatibility with other tools
 858      - Added PRIORITY parameter to $memwr cells
 859      - Added TRANSPARENT parameter to $memrd cells
 860      - Added RD_TRANSPARENT parameter to $mem cells
 861      - Added $bu0 cell (always 0-extend, even undef MSB)
 862      - Added $assert cell type
 863      - Added $slice and $concat cell types
 864
 865  * Integration with ABC:
 866      - Updated ABC to hg rev 2058c8ccea68
 867      - Tighter integration of ABC build with Yosys build. The make
 868            targets 'make abc' and 'make install-abc' are now obsolete.
 869      - Added support for passing FFs from one clock domain through ABC
 870      - Now always use BLIF as exchange format with ABC
 871      - Added support for "abc -script +<command_sequence>"
 872      - Improved standard ABC recipe
 873      - Added support for "keep" attribute to abc command
 874      - Added "abc -dff / -clk / -keepff" options
 875
 876  * Improvements to "eval" and "sat" framework:
 877      - Added support for "0" and "~0" in right-hand side -set expressions
 878      - Added "eval -set-undef" and "eval -table"
 879      - Added "sat -set-init" and "sat -set-init-*" for sequential problems
 880      - Added undef support to SAT solver, incl. various new "sat" options
 881      - Added correct support for === and !== for "eval" and "sat"
 882      - Added "sat -tempinduct" (default -seq is now non-induction sequential)
 883      - Added "sat -prove-asserts"
 884      - Complete rewrite of the 'freduce' command
 885      - Added "miter" command
 886      - Added "sat -show-inputs" and "sat -show-outputs"
 887      - Added "sat -ignore_unknown_cells" (now produce an error by default)
 888      - Added "sat -falsify"
 889      - Now "sat -verify" and "sat -falsify" can also be used without "-prove"
 890      - Added "expose" command
 891      - Added support for @<sel_name> to sat and eval signal expressions
 892
 893  * Changes in the 'make test' framework and auxiliary test tools:
 894      - Added autotest.sh -p and -f options
 895      - Replaced autotest.sh ISIM support with XSIM support
 896      - Added test cases for SAT framework
 897
 898  * Added "abbreviated IDs":
 899      - Now $<something>$foo can be abbreviated as $foo.
 900      - Usually this last part is a unique id (from RTLIL::autoidx)
 901      - This abbreviated IDs are now also used in "show" output
 902
 903  * Other changes to selection framework:
 904      - Now */ is optional in */<mode>:<arg> expressions
 905      - Added "select -assert-none" and "select -assert-any"
 906      - Added support for matching modules by attribute (A:<expr>)
 907      - Added "select -none"
 908      - Added support for r:<expr> pattern for matching cell parameters
 909      - Added support for !=, <, <=, >=, > for attribute and parameter matching
 910      - Added support for %s for selecting sub-modules
 911      - Added support for %m for expanding selections to whole modules
 912      - Added support for i:*, o:* and x:* pattern for selecting module ports
 913      - Added support for s:<expr> pattern for matching wire width
 914      - Added support for %a operation to select wire aliases
 915
 916  * Various other changes to commands and options:
 917      - The "ls" command now supports wildcards
 918      - Added "show -pause" and "show -format dot"
 919      - Added "show -color" support for cells
 920      - Added "show -label" and "show -notitle"
 921      - Added "dump -m" and "dump -n"
 922      - Added "history" command
 923      - Added "rename -hide"
 924      - Added "connect" command
 925      - Added "splitnets -driver"
 926      - Added "opt_const -mux_undef"
 927      - Added "opt_const -mux_bool"
 928      - Added "opt_const -undriven"
 929      - Added "opt -mux_undef -mux_bool -undriven -purge"
 930      - Added "hierarchy -libdir"
 931      - Added "hierarchy -purge_lib" (by default now do not remove lib cells)
 932      - Added "delete" command
 933      - Added "dump -append"
 934      - Added "setattr" and "setparam" commands
 935      - Added "design -stash/-copy-from/-copy-to"
 936      - Added "copy" command
 937      - Added "splice" command
 938