CHANGELOG

   1
   2 List of major changes and improvements between releases
   3 =======================================================
   4
   5 Yosys 0.10 .. Yosys 0.10-dev
   6 --------------------------
   7
   8  * Various
   9     - Added $aldff and $aldffe (flip-flops with async load) cells
  10
  11  * SystemVerilog
  12     - Fixed an issue which prevented writing directly to a memory word via a
  13       connection to an output port
  14     - Fixed an issue which prevented unbased unsized literals (e.g., `'1`) from
  15       filling the width of a cell input
  16     - Fixed an issue where connecting a slice covering the entirety of a signed
  17       signal to a cell input would cause a failed assertion
  18
  19 Yosys 0.9 .. Yosys 0.10
  20 --------------------------
  21
  22  * Various
  23     - Added automatic gzip decompression for frontends
  24     - Added $_NMUX_ cell type
  25     - Added automatic gzip compression (based on filename extension) for backends
  26     - Improve attribute and parameter encoding in JSON to avoid ambiguities between
  27       bit vectors and strings containing [01xz]*
  28     - Improvements in pmgen: subpattern and recursive matches
  29     - Support explicit FIRRTL properties
  30     - Improvements in pmgen: slices, choices, define, generate
  31     - Added "_TECHMAP_WIREINIT_*_" parameter and "_TECHMAP_REMOVEINIT_*_" wire for "techmap" pass
  32     - Added +/mul2dsp.v for decomposing wide multipliers to custom-sized ones
  33     - Added new frontend: rpc
  34     - Added --version and -version as aliases for -V
  35     - Improve yosys-smtbmc "solver not found" handling
  36     - Improved support of $readmem[hb] Memory Content File inclusion
  37     - Added CXXRTL backend
  38     - Use YosysHQ/abc instead of upstream berkeley-abc/abc
  39     - Added WASI platform support.
  40     - Added extmodule support to firrtl backend
  41     - Added $divfloor and $modfloor cells
  42     - Added $adffe, $dffsre, $sdff, $sdffe, $sdffce, $adlatch cells
  43     - Added "_TECHMAP_CELLNAME_" parameter for "techmap" pass
  44     - Added firrtl backend support for generic parameters in blackbox components
  45     - Added $meminit_v2 cells (with support for write mask)
  46     - Added $mem_v2, $memrd_v2, $memwr_v2, with the following features:
  47       - write priority masks, per write/write port pair
  48       - transparency and undefined collision behavior masks, per read/write port pair
  49       - read port reset and initialization
  50       - wide ports (accessing a naturally aligned power-of-two number of memory cells)
  51
  52  * New commands and options
  53     - Added "write_xaiger" backend
  54     - Added "read_xaiger"
  55     - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only)
  56     - Added "synth -abc9" (experimental)
  57     - Added "script -scriptwire"
  58     - Added "clkbufmap" pass
  59     - Added "extractinv" pass and "invertible_pin" attribute
  60     - Added "proc_clean -quiet"
  61     - Added "proc_prune" pass
  62     - Added "stat -tech cmos"
  63     - Added "opt_share" pass, run as part of "opt -full"
  64     - Added "-match-init" option to "dff2dffs" pass
  65     - Added "equiv_opt -multiclock"
  66     - Added "techmap_autopurge" support to techmap
  67     - Added "add -mod <modname[s]>"
  68     - Added "paramap" pass
  69     - Added "portlist" command
  70     - Added "check -mapped"
  71     - Added "check -allow-tbuf"
  72     - Added "autoname" pass
  73     - Added "write_verilog -extmem"
  74     - Added "opt_mem" pass
  75     - Added "scratchpad" pass
  76     - Added "fminit" pass
  77     - Added "opt_lut_ins" pass
  78     - Added "logger" pass
  79     - Added "show -nobg"
  80     - Added "exec" command
  81     - Added "design -delete"
  82     - Added "design -push-copy"
  83     - Added "qbfsat" command
  84     - Added "select -unset"
  85     - Added "dfflegalize" pass
  86     - Removed "opt_expr -clkinv" option, made it the default
  87     - Added "proc -nomux
  88     - Merged "dffsr2dff", "opt_rmdff", "dff2dffe", "dff2dffs", "peepopt.dffmux" passes into a new "opt_dff" pass
  89
  90  * SystemVerilog
  91     - Added checking of always block types (always_comb, always_latch and always_ff)
  92     - Added support for wildcard port connections (.*)
  93     - Added support for enum typedefs
  94     - Added support for structs and packed unions.
  95     - Allow constant function calls in for loops and generate if and case
  96     - Added support for static cast
  97     - Added support for logic typed parameters
  98     - Fixed generate scoping issues
  99     - Added support for real-valued parameters
 100     - Allow localparams in constant functions
 101     - Module name scope support
 102     - Support recursive functions using ternary expressions
 103     - Extended support for integer types
 104     - Support for parameters without default values
 105     - Allow globals in one file to depend on globals in another
 106     - Added support for: *=, /=, %=, <<=, >>=, <<<=, >>>=
 107     - Added support for parsing the 'bind' construct
 108     - support declaration in procedural for initialization
 109     - support declaration in generate for initialization
 110     - Support wand and wor of data types
 111
 112  * Verific support
 113     - Added "verific -L"
 114     - Add Verific SVA support for "always" properties
 115     - Add Verific support for SVA nexttime properties
 116     - Improve handling of verific primitives in "verific -import -V" mode
 117     - Import attributes for wires
 118     - Support VHDL enums
 119     - Added support for command files
 120
 121  * New back-ends
 122     - Added initial EFINIX support
 123     - Added Intel ALM: alternative synthesis for Intel FPGAs
 124     - Added initial Nexus support
 125     - Added initial MachXO2 support
 126     - Added initial QuickLogic PolarPro 3 support
 127
 128  * ECP5 support
 129     - Renamed labels/options in synth_ecp5 (e.g. dram -> map_lutram; -nodram -> -nolutram)
 130     - Added "synth_ecp5 -abc9" (experimental)
 131     - Added "synth_ecp5 -nowidelut"
 132     - "synth_ecp5" to now infer DSP blocks (-nodsp to disable, experimental)
 133
 134  * iCE40 support
 135     - Added "synth_ice40 -abc9" (experimental)
 136     - Added "synth_ice40 -device"
 137     - Renamed labels/options in synth_ice40 (e.g. dram -> map_lutram; -nodram -> -nolutram)
 138     - Added "ice40_wrapcarry" to encapsulate SB_LUT+SB_CARRY pairs for techmapping
 139     - Removed "ice40_unlut"
 140     - Added "ice40_dsp" for Lattice iCE40 DSP packing
 141     - "synth_ice40 -dsp" to infer DSP blocks
 142
 143  * Xilinx support
 144     - Added "synth_xilinx -abc9" (experimental)
 145     - Added "synth_xilinx -nocarry"
 146     - Added "synth_xilinx -nowidelut"
 147     - "synth_xilinx" to now infer wide multiplexers (-widemux <min> to enable)
 148     - Renamed labels/options in synth_xilinx (e.g. dram -> map_lutram; -nodram -> -nolutram)
 149     - Added "synth_xilinx -family xc6s" for Spartan 6 support (experimental)
 150     - Added "synth_xilinx -ise" (experimental)
 151     - Added "synth_xilinx -iopad"
 152     - "synth_xilinx" now automatically inserts clock buffers (add -noclkbuf to disable)
 153     - Added "xilinx_srl" for Xilinx shift register extraction
 154     - Removed "shregmap -tech xilinx" (superseded by "xilinx_srl")
 155     - Added "xilinx_dsp" for Xilinx DSP packing
 156     - "synth_xilinx" to now infer DSP blocks (-nodsp to disable)
 157     - Added latch support to synth_xilinx
 158     - Added support for flip-flops with synchronous reset to synth_xilinx
 159     - Added support for flip-flops with reset and enable to synth_xilinx
 160     - Added "xilinx_dffopt" pass
 161     - Added "synth_xilinx -dff"
 162
 163  * Intel support
 164     - Renamed labels in synth_intel (e.g. bram -> map_bram)
 165     - synth_intel: cyclone10 -> cyclone10lp, a10gx -> arria10gx
 166     - Added "intel_alm -abc9" (experimental)
 167
 168  * CoolRunner2 support
 169     - Separate and improve buffer cell insertion pass
 170     - Use extract_counter to optimize counters
 171
 172 Yosys 0.8 .. Yosys 0.9
 173 ----------------------
 174
 175  * Various
 176     - Many bugfixes and small improvements
 177     - Added support for SystemVerilog interfaces and modports
 178     - Added "write_edif -attrprop"
 179     - Added "opt_lut" pass
 180     - Added "gate2lut.v" techmap rule
 181     - Added "rename -src"
 182     - Added "equiv_opt" pass
 183     - Added "flowmap" LUT mapping pass
 184     - Added "rename -wire" to rename cells based on the wires they drive
 185     - Added "bugpoint" for creating minimised testcases
 186     - Added "write_edif -gndvccy"
 187     - "write_verilog" to escape Verilog keywords
 188     - Fixed sign handling of real constants
 189     - "write_verilog" to write initial statement for initial flop state
 190     - Added pmgen pattern matcher generator
 191     - Fixed opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_
 192     - Added "setundef -params" to replace undefined cell parameters
 193     - Renamed "yosys -D" to "yosys -U", added "yosys -D" to set Verilog defines
 194     - Fixed handling of defparam when default_nettype is none
 195     - Fixed "wreduce" flipflop handling
 196     - Fixed FIRRTL to Verilog process instance subfield assignment
 197     - Added "write_verilog -siminit"
 198     - Several fixes and improvements for mem2reg memories
 199     - Fixed handling of task output ports in clocked always blocks
 200     - Improved handling of and-with-1 and or-with-0 in "opt_expr"
 201     - Added "read_aiger" frontend
 202     - Added "mutate" pass
 203     - Added "hdlname" attribute
 204     - Added "rename -output"
 205     - Added "read_ilang -lib"
 206     - Improved "proc" full_case detection and handling
 207     - Added "whitebox" and "lib_whitebox" attributes
 208     - Added "read_verilog -nowb", "flatten -wb" and "wbflip"
 209     - Added Python bindings and support for Python plug-ins
 210     - Added "pmux2shiftx"
 211     - Added log_debug framework for reduced default verbosity
 212     - Improved "opt_expr" and "opt_clean" handling of (partially) undriven and/or unused wires
 213     - Added "peepopt" peephole optimisation pass using pmgen
 214     - Added approximate support for SystemVerilog "var" keyword
 215     - Added parsing of "specify" blocks into $specrule and $specify[23]
 216     - Added support for attributes on parameters and localparams
 217     - Added support for parsing attributes on port connections
 218     - Added "wreduce -keepdc"
 219     - Added support for optimising $dffe and $_DFFE_* cells in "opt_rmdff"
 220     - Added Verilog wand/wor wire type support
 221     - Added support for elaboration system tasks
 222     - Added "muxcover -mux{4,8,16}=<cost>"
 223     - Added "muxcover -dmux=<cost>"
 224     - Added "muxcover -nopartial"
 225     - Added "muxpack" pass
 226     - Added "pmux2shiftx -norange"
 227     - Added support for "~" in filename parsing
 228     - Added "read_verilog -pwires" feature to turn parameters into wires
 229     - Fixed sign extension of unsized constants with 'bx and 'bz MSB
 230     - Fixed genvar to be a signed type
 231     - Added support for attributes on case rules
 232     - Added "upto" and "offset" to JSON frontend and backend
 233     - Several liberty file parser improvements
 234     - Fixed handling of more complex BRAM patterns
 235     - Add "write_aiger -I -O -B"
 236
 237  * Formal Verification
 238     - Added $changed support to read_verilog
 239     - Added "read_verilog -noassert -noassume -assert-assumes"
 240     - Added btor ops for $mul, $div, $mod and $concat
 241     - Added yosys-smtbmc support for btor witnesses
 242     - Added "supercover" pass
 243     - Fixed $global_clock handling vs autowire
 244     - Added $dffsr support to "async2sync"
 245     - Added "fmcombine" pass
 246     - Added memory init support in "write_btor"
 247     - Added "cutpoint" pass
 248     - Changed "ne" to "neq" in btor2 output
 249     - Added support for SVA "final" keyword
 250     - Added "fmcombine -initeq -anyeq"
 251     - Added timescale and generated-by header to yosys-smtbmc vcd output
 252     - Improved BTOR2 handling of undriven wires
 253
 254  * Verific support
 255     - Enabled Verific flags vhdl_support_variable_slice and veri_elaborate_top_level_modules_having_interface_ports
 256     - Improved support for asymmetric memories
 257     - Added "verific -chparam"
 258     - Fixed "verific -extnets" for more complex situations
 259     - Added "read -verific" and "read -noverific"
 260     - Added "hierarchy -chparam"
 261
 262  * New back-ends
 263     - Added initial Anlogic support
 264     - Added initial SmartFusion2 and IGLOO2 support
 265
 266  * ECP5 support
 267     - Added "synth_ecp5 -nowidelut"
 268     - Added BRAM inference support to "synth_ecp5"
 269     - Added support for transforming Diamond IO and flipflop primitives
 270
 271  * iCE40 support
 272     - Added "ice40_unlut" pass
 273     - Added "synth_ice40 -relut"
 274     - Added "synth_ice40 -noabc"
 275     - Added "synth_ice40 -dffe_min_ce_use"
 276     - Added DSP inference support using pmgen
 277     - Added support for initialising BRAM primitives from a file
 278     - Added iCE40 Ultra RGB LED driver cells
 279
 280  * Xilinx support
 281     - Use "write_edif -pvector bra" for Xilinx EDIF files
 282     - Fixes for VPR place and route support with "synth_xilinx"
 283     - Added more cell simulation models
 284     - Added "synth_xilinx -family"
 285     - Added "stat -tech xilinx" to estimate logic cell usage
 286     - Added "synth_xilinx -nocarry"
 287     - Added "synth_xilinx -nowidelut"
 288     - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
 289     - Added support for mapping RAM32X1D
 290
 291 Yosys 0.7 .. Yosys 0.8
 292 ----------------------
 293
 294  * Various
 295     - Many bugfixes and small improvements
 296     - Strip debug symbols from installed binary
 297     - Replace -ignore_redef with -[no]overwrite in front-ends
 298     - Added write_verilog hex dump support, add -nohex option
 299     - Added "write_verilog -decimal"
 300     - Added "scc -set_attr"
 301     - Added "verilog_defines" command
 302     - Remember defines from one read_verilog to next
 303     - Added support for hierarchical defparam
 304     - Added FIRRTL back-end
 305     - Improved ABC default scripts
 306     - Added "design -reset-vlog"
 307     - Added "yosys -W regex", "yosys -w regex", and "yosys -e regex"
 308     - Added Verilog $rtoi and $itor support
 309     - Added "check -initdrv"
 310     - Added "read_blif -wideports"
 311     - Added support for SystemVerilog "++" and "--" operators
 312     - Added support for SystemVerilog unique, unique0, and priority case
 313     - Added "write_edif" options for edif "flavors"
 314     - Added support for resetall compiler directive
 315     - Added simple C beck-end (bitwise combinatorical only atm)
 316     - Added $_ANDNOT_ and $_ORNOT_ cell types
 317     - Added cell library aliases to "abc -g"
 318     - Added "setundef -anyseq"
 319     - Added "chtype" command
 320     - Added "design -import"
 321     - Added "write_table" command
 322     - Added "read_json" command
 323     - Added "sim" command
 324     - Added "extract_fa" and "extract_reduce" commands
 325     - Added "extract_counter" command
 326     - Added "opt_demorgan" command
 327     - Added support for $size and $bits SystemVerilog functions
 328     - Added "blackbox" command
 329     - Added "ltp" command
 330     - Added support for editline as replacement for readline
 331     - Added warnings for driver-driver conflicts between FFs (and other cells) and constants
 332     - Added "yosys -E" for creating Makefile dependencies files
 333     - Added "synth -noshare"
 334     - Added "memory_nordff"
 335     - Added "setundef -undef -expose -anyconst"
 336     - Added "expose -input"
 337     - Added specify/specparam parser support (simply ignore them)
 338     - Added "write_blif -inames -iattr"
 339     - Added "hierarchy -simcheck"
 340     - Added an option to statically link abc into yosys
 341     - Added protobuf back-end
 342     - Added BLIF parsing support for .conn and .cname
 343     - Added read_verilog error checking for reg/wire/logic misuse
 344     - Added "make coverage" and ENABLE_GCOV build option
 345
 346  * Changes in Yosys APIs
 347     - Added ConstEval defaultval feature
 348     - Added {get,set}_src_attribute() methods on RTLIL::AttrObject
 349     - Added SigSpec::is_fully_ones() and Const::is_fully_ones()
 350     - Added log_file_warning() and log_file_error() functions
 351
 352  * Formal Verification
 353     - Added "write_aiger"
 354     - Added "yosys-smtbmc --aig"
 355     - Added "always <positive_int>" to .smtc format
 356     - Added $cover cell type and support for cover properties
 357     - Added $fair/$live cell type and support for liveness properties
 358     - Added smtbmc support for memory vcd dumping
 359     - Added "chformal" command
 360     - Added "write_smt2 -stbv" and "write_smt2 -stdt"
 361     - Fix equiv_simple, old behavior now available with "equiv_simple -short"
 362     - Change to Yices2 as default SMT solver (it is GPL now)
 363     - Added "yosys-smtbmc --presat" (now default in SymbiYosys)
 364     - Added "yosys-smtbmc --smtc-init --smtc-top --noinit"
 365     - Added a brand new "write_btor" command for BTOR2
 366     - Added clk2fflogic memory support and other improvements
 367     - Added "async memory write" support to write_smt2
 368     - Simulate clock toggling in yosys-smtbmc VCD output
 369     - Added $allseq/$allconst cells for EA-solving
 370     - Make -nordff the default in "prep"
 371     - Added (* gclk *) attribute
 372     - Added "async2sync" pass for single-clock designs with async resets
 373
 374  * Verific support
 375     - Many improvements in Verific front-end
 376     - Added proper handling of concurent SVA properties
 377     - Map "const" and "rand const" to $anyseq/$anyconst
 378     - Added "verific -import -flatten" and "verific -import -extnets"
 379     - Added "verific -vlog-incdir -vlog-define -vlog-libdir"
 380     - Remove PSL support (because PSL has been removed in upstream Verific)
 381     - Improve integration with "hierarchy" command design elaboration
 382     - Added YOSYS_NOVERIFIC for running non-verific test cases with verific bin
 383     - Added simpilied "read" command that automatically uses verific if available
 384     - Added "verific -set-<severity> <msg_id>.."
 385     - Added "verific -work <libname>"
 386
 387  * New back-ends
 388     - Added initial Coolrunner-II support
 389     - Added initial eASIC support
 390     - Added initial ECP5 support
 391
 392  * GreenPAK Support
 393     - Added support for GP_DLATCH, GP_SPI, GP_DCMx, GP_COUNTx, etc.
 394
 395  * iCE40 Support
 396     - Add "synth_ice40 -vpr"
 397     - Add "synth_ice40 -nodffe"
 398     - Add "synth_ice40 -json"
 399     - Add Support for UltraPlus cells
 400
 401  * MAX10 and Cyclone IV Support
 402     - Added initial version of metacommand "synth_intel".
 403     - Improved write_verilog command to produce VQM netlist for Quartus Prime.
 404     - Added support for MAX10 FPGA family synthesis.
 405     - Added support for Cyclone IV family synthesis.
 406     - Added example of implementation for DE2i-150 board.
 407     - Added example of implementation for MAX10 development kit.
 408     - Added LFSR example from Asic World.
 409     - Added "dffinit -highlow" for mapping to Intel primitives
 410
 411
 412 Yosys 0.6 .. Yosys 0.7
 413 ----------------------
 414
 415  * Various
 416     - Added "yosys -D" feature
 417     - Added support for installed plugins in $(DATDIR)/plugins/
 418     - Renamed opt_const to opt_expr
 419     - Renamed opt_share to opt_merge
 420     - Added "prep -flatten" and "synth -flatten"
 421     - Added "prep -auto-top" and "synth -auto-top"
 422     - Using "mfs" and "lutpack" in ABC lut mapping
 423     - Support for abstract modules in chparam
 424     - Cleanup abstract modules at end of "hierarchy -top"
 425     - Added tristate buffer support to iopadmap
 426     - Added opt_expr support for div/mod by power-of-two
 427     - Added "select -assert-min <N> -assert-max <N>"
 428     - Added "attrmvcp" pass
 429     - Added "attrmap" command
 430     - Added "tee +INT -INT"
 431     - Added "zinit" pass
 432     - Added "setparam -type"
 433     - Added "shregmap" pass
 434     - Added "setundef -init"
 435     - Added "nlutmap -assert"
 436     - Added $sop cell type and "abc -sop -I <num> -P <num>"
 437     - Added "dc2" to default ABC scripts
 438     - Added "deminout"
 439     - Added "insbuf" command
 440     - Added "prep -nomem"
 441     - Added "opt_rmdff -keepdc"
 442     - Added "prep -nokeepdc"
 443     - Added initial version of "synth_gowin"
 444     - Added "fsm_expand -full"
 445     - Added support for fsm_encoding="user"
 446     - Many improvements in GreenPAK4 support
 447     - Added black box modules for all Xilinx 7-series lib cells
 448     - Added synth_ice40 support for latches via logic loops
 449     - Fixed ice40_opt lut unmapping, added "ice40_opt -unlut"
 450
 451  * Build System
 452     - Added ABCEXTERNAL and ABCURL make variables
 453     - Added BINDIR, LIBDIR, and DATDIR make variables
 454     - Added PKG_CONFIG make variable
 455     - Added SEED make variable (for "make test")
 456     - Added YOSYS_VER_STR make variable
 457     - Updated min GCC requirement to GCC 4.8
 458     - Updated required Bison version to Bison 3.x
 459
 460  * Internal APIs
 461     - Added ast.h to exported headers
 462     - Added ScriptPass helper class for script-like passes
 463     - Added CellEdgesDatabase API
 464
 465  * Front-ends and Back-ends
 466     - Added filename glob support to all front-ends
 467     - Added avail (black-box) module params to ilang format
 468     - Added $display %m support
 469     - Added support for $stop Verilog system task
 470     - Added support for SystemVerilog packages
 471     - Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b}
 472     - Added support for "active high" and "active low" latches in read_blif and write_blif
 473     - Use init value "2" for all uninitialized FFs in BLIF back-end
 474     - Added "read_blif -sop"
 475     - Added "write_blif -noalias"
 476     - Added various write_blif options for VTR support
 477     - write_json: also write module attributes.
 478     - Added "write_verilog -nodec -nostr -defparam"
 479     - Added "read_verilog -norestrict -assume-asserts"
 480     - Added support for bus interfaces to "read_liberty -lib"
 481     - Added liberty parser support for types within cell decls
 482     - Added "write_verilog -renameprefix -v"
 483     - Added "write_edif -nogndvcc"
 484
 485  * Formal Verification
 486     - Support for hierarchical designs in smt2 back-end
 487     - Yosys-smtbmc: Support for hierarchical VCD dumping
 488     - Added $initstate cell type and vlog function
 489     - Added $anyconst and $anyseq cell types and vlog functions
 490     - Added printing of code loc of failed asserts to yosys-smtbmc
 491     - Added memory_memx pass, "memory -memx", and "prep -memx"
 492     - Added "proc_mux -ifx"
 493     - Added "yosys-smtbmc -g"
 494     - Deprecated "write_smt2 -regs" (by default on now)
 495     - Made "write_smt2 -bv -mem" default, added "write_smt2 -nobv -nomem"
 496     - Added support for memories to smtio.py
 497     - Added "yosys-smtbmc --dump-vlogtb"
 498     - Added "yosys-smtbmc --smtc --dump-smtc"
 499     - Added "yosys-smtbmc --dump-all"
 500     - Added assertpmux command
 501     - Added "yosys-smtbmc --unroll"
 502     - Added $past, $stable, $rose, $fell SVA functions
 503     - Added "yosys-smtbmc --noinfo and --dummy"
 504     - Added "yosys-smtbmc --noincr"
 505     - Added "yosys-smtbmc --cex <filename>"
 506     - Added $ff and $_FF_ cell types
 507     - Added $global_clock verilog syntax support for creating $ff cells
 508     - Added clk2fflogic
 509
 510
 511 Yosys 0.5 .. Yosys 0.6
 512 ----------------------
 513
 514  * Various
 515      - Added Contributor Covenant Code of Conduct
 516      - Various improvements in dict<> and pool<>
 517      - Added hashlib::mfp and refactored SigMap
 518      - Improved support for reals as module parameters
 519      - Various improvements in SMT2 back-end
 520      - Added "keep_hierarchy" attribute
 521      - Verilog front-end: define `BLACKBOX in -lib mode
 522      - Added API for converting internal cells to AIGs
 523      - Added ENABLE_LIBYOSYS Makefile option
 524      - Removed "techmap -share_map" (use "-map +/filename" instead)
 525      - Switched all Python scripts to Python 3
 526      - Added support for $display()/$write() and $finish() to Verilog front-end
 527      - Added "yosys-smtbmc" formal verification flow
 528      - Added options for clang sanitizers to Makefile
 529
 530  * New commands and options
 531      - Added "scc -expect <N> -nofeedback"
 532      - Added "proc_dlatch"
 533      - Added "check"
 534      - Added "select %xe %cie %coe %M %C %R"
 535      - Added "sat -dump_json" (WaveJSON format)
 536      - Added "sat -tempinduct-baseonly -tempinduct-inductonly"
 537      - Added "sat -stepsize" and "sat -tempinduct-step"
 538      - Added "sat -show-regs -show-public -show-all"
 539      - Added "write_json" (Native Yosys JSON format)
 540      - Added "write_blif -attr"
 541      - Added "dffinit"
 542      - Added "chparam"
 543      - Added "muxcover"
 544      - Added "pmuxtree"
 545      - Added memory_bram "make_outreg" feature
 546      - Added "splice -wires"
 547      - Added "dff2dffe -direct-match"
 548      - Added simplemap $lut support
 549      - Added "read_blif"
 550      - Added "opt_share -share_all"
 551      - Added "aigmap"
 552      - Added "write_smt2 -mem -regs -wires"
 553      - Added "memory -nordff"
 554      - Added "write_smv"
 555      - Added "synth -nordff -noalumacc"
 556      - Added "rename -top new_name"
 557      - Added "opt_const -clkinv"
 558      - Added "synth -nofsm"
 559      - Added "miter -assert"
 560      - Added "read_verilog -noautowire"
 561      - Added "read_verilog -nodpi"
 562      - Added "tribuf"
 563      - Added "lut2mux"
 564      - Added "nlutmap"
 565      - Added "qwp"
 566      - Added "test_cell -noeval"
 567      - Added "edgetypes"
 568      - Added "equiv_struct"
 569      - Added "equiv_purge"
 570      - Added "equiv_mark"
 571      - Added "equiv_add -try -cell"
 572      - Added "singleton"
 573      - Added "abc -g -luts"
 574      - Added "torder"
 575      - Added "write_blif -cname"
 576      - Added "submod -copy"
 577      - Added "dffsr2dff"
 578      - Added "stat -liberty"
 579
 580  * Synthesis metacommands
 581      - Various improvements in synth_xilinx
 582      - Added synth_ice40 and synth_greenpak4
 583      - Added "prep" metacommand for "synthesis lite"
 584
 585  * Cell library changes
 586      - Added cell types to "help" system
 587      - Added $meminit cell type
 588      - Added $assume cell type
 589      - Added $_MUX4_, $_MUX8_, and $_MUX16_ cells
 590      - Added $tribuf and $_TBUF_ cell types
 591      - Added read-enable to memory model
 592
 593  * YosysJS
 594      - Various improvements in emscripten build
 595      - Added alternative webworker-based JS API
 596      - Added a few example applications
 597
 598
 599 Yosys 0.4 .. Yosys 0.5
 600 ----------------------
 601
 602  * API changes
 603      - Added log_warning()
 604      - Added eval_select_args() and eval_select_op()
 605      - Added cell->known(), cell->input(portname), cell->output(portname)
 606      - Skip blackbox modules in design->selected_modules()
 607      - Replaced std::map<> and std::set<> with dict<> and pool<>
 608      - New SigSpec::extend() is what used to be SigSpec::extend_u0()
 609      - Added YS_OVERRIDE, YS_FINAL, YS_ATTRIBUTE, YS_NORETURN
 610
 611  * Cell library changes
 612      - Added flip-flops with enable ($dffe etc.)
 613      - Added $equiv cells for equivalence checking framework
 614
 615  * Various
 616      - Updated ABC to hg rev 61ad5f908c03
 617      - Added clock domain partitioning to ABC pass
 618      - Improved plugin building (see "yosys-config --build")
 619      - Added ENABLE_NDEBUG Makefile flag for high-performance builds
 620      - Added "yosys -d", "yosys -L" and other driver improvements
 621      - Added support for multi-bit (array) cell ports to "write_edif"
 622      - Now printing most output to stdout, not stderr
 623      - Added "onehot" attribute (set by "fsm_map")
 624      - Various performance improvements
 625      - Vastly improved Xilinx flow
 626      - Added "make unsintall"
 627
 628  * Equivalence checking
 629      - Added equivalence checking commands:
 630          equiv_make equiv_simple equiv_status
 631          equiv_induct equiv_miter
 632          equiv_add equiv_remove
 633
 634  * Block RAM support:
 635      - Added "memory_bram" command
 636      - Added BRAM support to Xilinx flow
 637
 638  * Other New Commands and Options
 639      - Added "dff2dffe"
 640      - Added "fsm -encfile"
 641      - Added "dfflibmap -prepare"
 642      - Added "write_blid -unbuf -undef -blackbox"
 643      - Added "write_smt2" for writing SMT-LIBv2 files
 644      - Added "test_cell -w -muxdiv"
 645      - Added "select -read"
 646
 647
 648 Yosys 0.3.0 .. Yosys 0.4
 649 ------------------------
 650
 651  * Platform Support
 652      - Added support for mxe-based cross-builds for win32
 653      - Added sourcecode-export as VisualStudio project
 654      - Added experimental EMCC (JavaScript) support
 655
 656  * Verilog Frontend
 657      - Added -sv option for SystemVerilog (and automatic *.sv file support)
 658      - Added support for real-valued constants and constant expressions
 659      - Added support for non-standard "via_celltype" attribute on task/func
 660      - Added support for non-standard "module mod_name(...);" syntax
 661      - Added support for non-standard """ macro bodies
 662      - Added support for array with more than one dimension
 663      - Added support for $readmemh and $readmemb
 664      - Added support for DPI functions
 665
 666  * Changes in internal cell library
 667      - Added $shift and $shiftx cell types
 668      - Added $alu, $lcu, $fa and $macc cell types
 669      - Removed $bu0 and $safe_pmux cell types
 670      - $mem/$memwr WR_EN input is now a per-data-bit enable signal
 671      - Added $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
 672      - Renamed ports of $lut cells (from I->O to A->Y)
 673      - Renamed $_INV_ to $_NOT_
 674
 675  * Changes for simple synthesis flows
 676      - There is now a "synth" command with a recommended default script
 677      - Many improvements in synthesis of arithmetic functions to gates
 678          - Multipliers and adders with many operands are using carry-save adder trees
 679          - Remaining adders are now implemented using Brent-Kung carry look-ahead adders
 680      - Various new high-level optimizations on RTL netlist
 681      - Various improvements in FSM optimization
 682      - Updated ABC to hg 5b5af75f1dda (from 2014-11-07)
 683
 684  * Changes in internal APIs and RTLIL
 685      - Added log_id() and log_cell() helper functions
 686      - Added function-like cell creation helpers
 687      - Added GetSize() function (like .size() but with int)
 688      - Major refactoring of RTLIL::Module and related classes
 689      - Major refactoring of RTLIL::SigSpec and related classes
 690      - Now RTLIL::IdString is essentially an int
 691      - Added macros for code coverage counters
 692      - Added some Makefile magic for pretty make logs
 693      - Added "kernel/yosys.h" with all the core definitions
 694      - Changed a lot of code from FILE* to c++ streams
 695      - Added RTLIL::Monitor API and "trace" command
 696      - Added "Yosys" C++ namespace
 697
 698  * Changes relevant to SAT solving
 699      - Added ezSAT::keep_cnf() and ezSAT::non_incremental()
 700      - Added native ezSAT support for vector shift ops
 701      - Updated MiniSAT to git 37dc6c67e2 (from 2013-09-25)
 702
 703  * New commands (or large improvements to commands)
 704      - Added "synth" command with default script
 705      - Added "share" (finally some real resource sharing)
 706      - Added "memory_share" (reduce number of ports on memories)
 707      - Added "wreduce" and "alumacc" commands
 708      - Added "opt -keepdc -fine -full -fast"
 709      - Added some "test_*" commands
 710
 711  * Various other changes
 712      - Added %D and %c select operators
 713      - Added support for labels in yosys scripts
 714      - Added support for here-documents in yosys scripts
 715      - Support "+/" prefix for files from proc_share_dir
 716      - Added "autoidx" statement to ilang language
 717      - Switched from "yosys-svgviewer" to "xdot"
 718      - Renamed "stdcells.v" to "techmap.v"
 719      - Various bug fixes and small improvements
 720      - Improved welcome and bye messages
 721
 722
 723 Yosys 0.2.0 .. Yosys 0.3.0
 724 --------------------------
 725
 726  * Driver program and overall behavior:
 727      - Added "design -push" and "design -pop"
 728      - Added "tee" command for redirecting log output
 729
 730  * Changes in the internal cell library:
 731      - Added $dlatchsr and $_DLATCHSR_???_ cell types
 732
 733  * Improvements in Verilog frontend:
 734      - Improved support for const functions (case, always, repeat)
 735      - The generate..endgenerate keywords are now optional
 736      - Added support for arrays of module instances
 737      - Added support for "`default_nettype" directive
 738      - Added support for "`line" directive
 739
 740  * Other front- and back-ends:
 741      - Various changes to "write_blif" options
 742      - Various improvements in EDIF backend
 743      - Added "vhdl2verilog" pseudo-front-end
 744      - Added "verific" pseudo-front-end
 745
 746  * Improvements in technology mapping:
 747      - Added support for recursive techmap
 748      - Added CONSTMSK and CONSTVAL features to techmap
 749      - Added _TECHMAP_CONNMAP_*_ feature to techmap
 750      - Added _TECHMAP_REPLACE_ feature to techmap
 751      - Added "connwrappers" command for wrap-extract-unwrap method
 752      - Added "extract -map %<design_name>" feature
 753      - Added "extract -ignore_param ..." and "extract -ignore_parameters"
 754      - Added "techmap -max_iter" option
 755
 756  * Improvements to "eval" and "sat" framework:
 757      - Now include a copy of Minisat (with build fixes applied)
 758      - Switched to Minisat::SimpSolver as SAT back-end
 759      - Added "sat -dump_vcd" feature
 760      - Added "sat -dump_cnf" feature
 761      - Added "sat -initsteps <N>" feature
 762      - Added "freduce -stop <N>" feature
 763      - Added "freduce -dump <prefix>" feature
 764
 765  * Integration with ABC:
 766      - Updated ABC rev to 7600ffb9340c
 767
 768  * Improvements in the internal APIs:
 769      - Added RTLIL::Module::add... helper methods
 770      - Various build fixes for OSX (Darwin) and OpenBSD
 771
 772
 773 Yosys 0.1.0 .. Yosys 0.2.0
 774 --------------------------
 775
 776  * Changes to the driver program:
 777      - Added "yosys -h" and "yosys -H"
 778      - Added support for backslash line continuation in scripts
 779      - Added support for #-comments in same line as command
 780      - Added "echo" and "log" commands
 781
 782  * Improvements in Verilog frontend:
 783      - Added support for local registers in named blocks
 784      - Added support for "case" in "generate" blocks
 785      - Added support for $clog2 system function
 786      - Added support for basic SystemVerilog assert statements
 787      - Added preprocessor support for macro arguments
 788      - Added preprocessor support for `elsif statement
 789      - Added "verilog_defaults" command
 790      - Added read_verilog -icells option
 791      - Added support for constant sizes from parameters
 792      - Added "read_verilog -setattr"
 793      - Added support for function returning 'integer'
 794      - Added limited support for function calls in parameter values
 795      - Added "read_verilog -defer" to suppress evaluation of modules with default parameters
 796
 797  * Other front- and back-ends:
 798      - Added BTOR backend
 799      - Added Liberty frontend
 800
 801  * Improvements in technology mapping:
 802      - The "dfflibmap" command now strongly prefers solutions with
 803            no inverters in clock paths
 804      - The "dfflibmap" command now prefers cells with smaller area
 805      - Added support for multiple -map options to techmap
 806      - Added "dfflibmap" support for //-comments in liberty files
 807      - Added "memory_unpack" command to revert "memory_collect"
 808      - Added standard techmap rule "techmap -share_map pmux2mux.v"
 809      - Added "iopadmap -bits"
 810      - Added "setundef" command
 811      - Added "hilomap" command
 812
 813  * Changes in the internal cell library:
 814      - Major rewrite of simlib.v for better compatibility with other tools
 815      - Added PRIORITY parameter to $memwr cells
 816      - Added TRANSPARENT parameter to $memrd cells
 817      - Added RD_TRANSPARENT parameter to $mem cells
 818      - Added $bu0 cell (always 0-extend, even undef MSB)
 819      - Added $assert cell type
 820      - Added $slice and $concat cell types
 821
 822  * Integration with ABC:
 823      - Updated ABC to hg rev 2058c8ccea68
 824      - Tighter integration of ABC build with Yosys build. The make
 825            targets 'make abc' and 'make install-abc' are now obsolete.
 826      - Added support for passing FFs from one clock domain through ABC
 827      - Now always use BLIF as exchange format with ABC
 828      - Added support for "abc -script +<command_sequence>"
 829      - Improved standard ABC recipe
 830      - Added support for "keep" attribute to abc command
 831      - Added "abc -dff / -clk / -keepff" options
 832
 833  * Improvements to "eval" and "sat" framework:
 834      - Added support for "0" and "~0" in right-hand side -set expressions
 835      - Added "eval -set-undef" and "eval -table"
 836      - Added "sat -set-init" and "sat -set-init-*" for sequential problems
 837      - Added undef support to SAT solver, incl. various new "sat" options
 838      - Added correct support for === and !== for "eval" and "sat"
 839      - Added "sat -tempinduct" (default -seq is now non-induction sequential)
 840      - Added "sat -prove-asserts"
 841      - Complete rewrite of the 'freduce' command
 842      - Added "miter" command
 843      - Added "sat -show-inputs" and "sat -show-outputs"
 844      - Added "sat -ignore_unknown_cells" (now produce an error by default)
 845      - Added "sat -falsify"
 846      - Now "sat -verify" and "sat -falsify" can also be used without "-prove"
 847      - Added "expose" command
 848      - Added support for @<sel_name> to sat and eval signal expressions
 849
 850  * Changes in the 'make test' framework and auxiliary test tools:
 851      - Added autotest.sh -p and -f options
 852      - Replaced autotest.sh ISIM support with XSIM support
 853      - Added test cases for SAT framework
 854
 855  * Added "abbreviated IDs":
 856      - Now $<something>$foo can be abbreviated as $foo.
 857      - Usually this last part is a unique id (from RTLIL::autoidx)
 858      - This abbreviated IDs are now also used in "show" output
 859
 860  * Other changes to selection framework:
 861      - Now */ is optional in */<mode>:<arg> expressions
 862      - Added "select -assert-none" and "select -assert-any"
 863      - Added support for matching modules by attribute (A:<expr>)
 864      - Added "select -none"
 865      - Added support for r:<expr> pattern for matching cell parameters
 866      - Added support for !=, <, <=, >=, > for attribute and parameter matching
 867      - Added support for %s for selecting sub-modules
 868      - Added support for %m for expanding selections to whole modules
 869      - Added support for i:*, o:* and x:* pattern for selecting module ports
 870      - Added support for s:<expr> pattern for matching wire width
 871      - Added support for %a operation to select wire aliases
 872
 873  * Various other changes to commands and options:
 874      - The "ls" command now supports wildcards
 875      - Added "show -pause" and "show -format dot"
 876      - Added "show -color" support for cells
 877      - Added "show -label" and "show -notitle"
 878      - Added "dump -m" and "dump -n"
 879      - Added "history" command
 880      - Added "rename -hide"
 881      - Added "connect" command
 882      - Added "splitnets -driver"
 883      - Added "opt_const -mux_undef"
 884      - Added "opt_const -mux_bool"
 885      - Added "opt_const -undriven"
 886      - Added "opt -mux_undef -mux_bool -undriven -purge"
 887      - Added "hierarchy -libdir"
 888      - Added "hierarchy -purge_lib" (by default now do not remove lib cells)
 889      - Added "delete" command
 890      - Added "dump -append"
 891      - Added "setattr" and "setparam" commands
 892      - Added "design -stash/-copy-from/-copy-to"
 893      - Added "copy" command
 894      - Added "splice" command
 895