CHANGES

   1 [> 2020.XX, planned for July 2020
   2 ---------------------------------
   3
   4         [> Issues resolved
   5         ------------------
   6         - Fix flush_cpu_icache on VexRiscv.
   7
   8         [> Added Features
   9         ------------------
  10         - BIOS history, autocomplete.
  11         - Pluggable CPUs.
  12         - Add nMigen dependency.
  13         - Properly integrate Minerva CPU.
  14
  15         [> API changes/Deprecation
  16         --------------------------
  17         - NA
  18
  19
  20 [> 2020.04, released April 28th, 2020
  21 -------------------------------------
  22
  23         [> Description
  24         --------------
  25         First release of LiteX and the ecosystem of cores!
  26
  27         LiteX is a Migen/MiSoC based Core/SoC builder that provides the infrastructure to easily create
  28         Cores/SoCs (with or without CPU).
  29
  30         The common components of a SoC are provided directly:
  31         - Buses and Streams (Wishbone, AXI, Avalon-ST)
  32         - Interconnect
  33         - Common cores (RAM, ROM, Timer, UART, etc...)
  34         - CPU wrappers/integration
  35         - etc...
  36         And SoC creation capabilities can be greatly extended with the ecosystem of LiteX cores (DRAM,
  37         PCIe, Ethernet, SATA, etc...) that can be integrated/simulated/build easily with LiteX.
  38
  39         It also provides build backends for open-source and vendors toolchains.
  40
  41         [> Issues resolved
  42         ------------------
  43         - NA
  44
  45         [> Added Features
  46         ------------------
  47         - NA
  48
  49         [> API changes/Deprecation
  50         --------------------------
  51         - https://github.com/enjoy-digital/litex/pull/399: Converting LiteX to use Python modules.