CHANGES

   1 [> 2020.XX, planned for July 2020
   2 ---------------------------------
   3
   4         [> Issues resolved
   5         ------------------
   6         - Fix flush_cpu_icache on VexRiscv.
   7
   8         [> Added Features
   9         ------------------
  10         - Properly integrate Minerva CPU.
  11         - Add nMigen dependency.
  12         - Pluggable CPUs.
  13         - BIOS history, autocomplete.
  14         - Improve boards's programmers.
  15         - Add Microwatt CPU support (with GHDL-Yosys-plugin support for FOSS toolchains).
  16         - Speedup Memtest using an LFSR.
  17         - Add LedChaser on boards.
  18         - Improve WishboneBridge.
  19         - Improve Diamond constraints.
  20         - Use InterconnectPointToPoint when 1 master,1 slave and no address translation.
  21         - Add CV32E40P CPU support (ex RI5CY).
  22         - JTAG UART with uart_name=jtag_uart (validated on Spartan6, 7-Series, Ultrascale(+)).
  23         - Add Symbiflow experimental support on Arty.
  24         - Add SDCard boot from FAT/exFAT filesystems with FatFs.
  25         - Simplify boot with boot.json configuration file.
  26
  27         [> API changes/Deprecation
  28         --------------------------
  29         - Add --build --load arguments to targets.
  30         - Deprecate soc.interconnect.wishbone.UpConverter (will be rewritten if useful).
  31         - Deprecate soc.interconnect.wishbone.CSRBank (Does not seem to be used by anyone).
  32         - Move soc.interconnect.wishbone2csr.WB2CSR to soc.interconnect.wishbone.Wishbone2CSR.
  33         - Move soc.interconnect.wishbonebridge.WishboneStreamingBridge to soc.cores.uart.Stream2Wishbone.
  34         - Rename --gateware-toolchain target parameter to --toolchain.
  35
  36 [> 2020.04, released April 28th, 2020
  37 -------------------------------------
  38
  39         [> Description
  40         --------------
  41         First release of LiteX and the ecosystem of cores!
  42
  43         LiteX is a Migen/MiSoC based Core/SoC builder that provides the infrastructure to easily create
  44         Cores/SoCs (with or without CPU).
  45
  46         The common components of a SoC are provided directly:
  47         - Buses and Streams (Wishbone, AXI, Avalon-ST)
  48         - Interconnect
  49         - Common cores (RAM, ROM, Timer, UART, etc...)
  50         - CPU wrappers/integration
  51         - etc...
  52         And SoC creation capabilities can be greatly extended with the ecosystem of LiteX cores (DRAM,
  53         PCIe, Ethernet, SATA, etc...) that can be integrated/simulated/build easily with LiteX.
  54
  55         It also provides build backends for open-source and vendors toolchains.
  56
  57         [> Issues resolved
  58         ------------------
  59         - NA
  60
  61         [> Added Features
  62         ------------------
  63         - NA
  64
  65         [> API changes/Deprecation
  66         --------------------------
  67         - https://github.com/enjoy-digital/litex/pull/399: Converting LiteX to use Python modules.