CHANGES

   1 [> 2020.XX, planned for July 2020
   2 ---------------------------------
   3
   4         [> Issues resolved
   5         ------------------
   6         - Fix flush_cpu_icache on VexRiscv.
   7
   8         [> Added Features
   9         ------------------
  10         - JTAG UART with uart_name=jtag_uart (validated on Spartan6, 7-Series, Ultrascale(+)).
  11         - Add CV32E40P CPU support (ex RI5CY).
  12         - Use InterconnectPointToPoint when 1 master,1 slave and no address translation.
  13         - Improve WishboneBridge.
  14         - Improve Diamond constraints.
  15         - Add LedChaser on boards.
  16         - Speedup Memtest using an LFSR.
  17         - Add Microwatt CPU support (with GHDL-Yosys-plugin support for FOSS toolchains).
  18         - Improve boards's programmers.
  19         - BIOS history, autocomplete.
  20         - Pluggable CPUs.
  21         - Add nMigen dependency.
  22         - Properly integrate Minerva CPU.
  23
  24         [> API changes/Deprecation
  25         --------------------------
  26         - Add --build --load arguments to targets.
  27         - Deprecate soc.interconnect.wishbone.UpConverter (will be rewritten if useful).
  28         - Deprecate soc.interconnect.wishbone.CSRBank (Does not seem to be used by anyone).
  29         - Move soc.interconnect.wishbone2csr.WB2CSR to soc.interconnect.wishbone.Wishbone2CSR.
  30         - Move soc.interconnect.wishbonebridge.WishboneStreamingBridge to soc.cores.uart.Stream2Wishbone.
  31
  32 [> 2020.04, released April 28th, 2020
  33 -------------------------------------
  34
  35         [> Description
  36         --------------
  37         First release of LiteX and the ecosystem of cores!
  38
  39         LiteX is a Migen/MiSoC based Core/SoC builder that provides the infrastructure to easily create
  40         Cores/SoCs (with or without CPU).
  41
  42         The common components of a SoC are provided directly:
  43         - Buses and Streams (Wishbone, AXI, Avalon-ST)
  44         - Interconnect
  45         - Common cores (RAM, ROM, Timer, UART, etc...)
  46         - CPU wrappers/integration
  47         - etc...
  48         And SoC creation capabilities can be greatly extended with the ecosystem of LiteX cores (DRAM,
  49         PCIe, Ethernet, SATA, etc...) that can be integrated/simulated/build easily with LiteX.
  50
  51         It also provides build backends for open-source and vendors toolchains.
  52
  53         [> Issues resolved
  54         ------------------
  55         - NA
  56
  57         [> Added Features
  58         ------------------
  59         - NA
  60
  61         [> API changes/Deprecation
  62         --------------------------
  63         - https://github.com/enjoy-digital/litex/pull/399: Converting LiteX to use Python modules.