1 [> 2020.XX, planned for July 2020
2 ---------------------------------
6 - Fix flush_cpu_icache on VexRiscv.
10 - Add CV32E40P CPU support (ex RI5CY).
11 - Use InterconnectPointToPoint when 1 master,1 slave and no address translation.
12 - Improve WishboneBridge.
13 - Improve Diamond constraints.
14 - Add LedChaser on boards.
15 - Speedup Memtest using an LFSR.
16 - Add Microwatt CPU support (with GHDL-Yosys-plugin support for FOSS toolchains).
17 - Improve boards's programmers.
18 - BIOS history, autocomplete.
20 - Add nMigen dependency.
21 - Properly integrate Minerva CPU.
23 [> API changes/Deprecation
24 --------------------------
25 - Add --build --load arguments to targets.
28 [> 2020.04, released April 28th, 2020
29 -------------------------------------
33 First release of LiteX and the ecosystem of cores!
35 LiteX is a Migen/MiSoC based Core/SoC builder that provides the infrastructure to easily create
36 Cores/SoCs (with or without CPU).
38 The common components of a SoC are provided directly:
39 - Buses and Streams (Wishbone, AXI, Avalon-ST)
41 - Common cores (RAM, ROM, Timer, UART, etc...)
42 - CPU wrappers/integration
44 And SoC creation capabilities can be greatly extended with the ecosystem of LiteX cores (DRAM,
45 PCIe, Ethernet, SATA, etc...) that can be integrated/simulated/build easily with LiteX.
47 It also provides build backends for open-source and vendors toolchains.
57 [> API changes/Deprecation
58 --------------------------
59 - https://github.com/enjoy-digital/litex/pull/399: Converting LiteX to use Python modules.