Makefile

   1 GHDL ?= ghdl
   2 GHDLFLAGS=--std=08 -frelaxed
   3 CFLAGS=-O3 -Wall
   4
   5 GHDLSYNTH ?= ghdl.so
   6 YOSYS     ?= yosys
   7 NEXTPNR   ?= nextpnr-ecp5
   8 ECPPACK   ?= ecppack
   9 OPENOCD   ?= openocd
  10
  11 # We need a version of GHDL built with either the LLVM or gcc backend.
  12 # Fedora provides this, but other distros may not. Another option is to use
  13 # the Docker image.
  14 DOCKER ?= 0
  15 PODMAN ?= 0
  16
  17 ifeq ($(DOCKER), 1)
  18 DOCKERBIN=docker
  19 USE_DOCKER=1
  20 endif
  21
  22 ifeq ($(PODMAN), 1)
  23 DOCKERBIN=podman
  24 USE_DOCKER=1
  25 endif
  26
  27 ifeq ($(USE_DOCKER), 1)
  28 PWD = $(shell pwd)
  29 DOCKERARGS = run --rm -v $(PWD):/src:z -w /src
  30 GHDL      = $(DOCKERBIN) $(DOCKERARGS) ghdl/ghdl:buster-llvm-7 ghdl
  31 CC        = $(DOCKERBIN) $(DOCKERARGS) ghdl/ghdl:buster-llvm-7 gcc
  32 GHDLSYNTH = ghdl
  33 YOSYS     = $(DOCKERBIN) $(DOCKERARGS) hdlc/ghdl:yosys yosys
  34 NEXTPNR   = $(DOCKERBIN) $(DOCKERARGS) hdlc/nextpnr:ecp5 nextpnr-ecp5
  35 ECPPACK   = $(DOCKERBIN) $(DOCKERARGS) hdlc/prjtrellis ecppack
  36 OPENOCD   = $(DOCKERBIN) $(DOCKERARGS) --device /dev/bus/usb hdlc/prog openocd
  37 endif
  38
  39 all = core_tb icache_tb dcache_tb multiply_tb dmi_dtm_tb divider_tb \
  40         rotator_tb countzero_tb wishbone_bram_tb soc_reset_tb
  41
  42 all: $(all)
  43
  44 core_files = decode_types.vhdl common.vhdl wishbone_types.vhdl fetch1.vhdl \
  45         utils.vhdl plru.vhdl cache_ram.vhdl icache.vhdl \
  46         decode1.vhdl helpers.vhdl insn_helpers.vhdl \
  47         control.vhdl decode2.vhdl register_file.vhdl \
  48         cr_file.vhdl crhelpers.vhdl ppc_fx_insns.vhdl rotator.vhdl \
  49         logical.vhdl countzero.vhdl multiply.vhdl divider.vhdl execute1.vhdl \
  50         loadstore1.vhdl mmu.vhdl dcache.vhdl writeback.vhdl core_debug.vhdl \
  51         core.vhdl fpu.vhdl
  52
  53 soc_files = wishbone_arbiter.vhdl wishbone_bram_wrapper.vhdl sync_fifo.vhdl \
  54         wishbone_debug_master.vhdl xics.vhdl syscon.vhdl soc.vhdl \
  55         spi_rxtx.vhdl spi_flash_ctrl.vhdl
  56
  57 uart_files = $(wildcard uart16550/*.v)
  58
  59 soc_sim_files = $(core_files) $(soc_files) sim_console.vhdl sim_pp_uart.vhdl sim_bram_helpers.vhdl \
  60         sim_bram.vhdl sim_jtag_socket.vhdl sim_jtag.vhdl dmi_dtm_xilinx.vhdl \
  61         sim_16550_uart.vhdl \
  62         random.vhdl glibc_random.vhdl glibc_random_helpers.vhdl
  63
  64 soc_sim_c_files = sim_vhpi_c.c sim_bram_helpers_c.c sim_console_c.c \
  65         sim_jtag_socket_c.c
  66
  67 soc_sim_obj_files=$(soc_sim_c_files:.c=.o)
  68 comma := ,
  69 soc_sim_link=$(patsubst %,-Wl$(comma)%,$(soc_sim_obj_files))
  70
  71 unisim_dir = sim-unisim
  72 unisim_lib = $(unisim_dir)/unisim-obj08.cf
  73 unisim_lib_files = $(unisim_dir)/BSCANE2.vhdl $(unisim_dir)/BUFG.vhdl \
  74         $(unisim_dir)/unisim_vcomponents.vhdl
  75 $(unisim_lib): $(unisim_lib_files)
  76         $(GHDL) -i --std=08 --work=unisim --workdir=$(unisim_dir) $^
  77 GHDLFLAGS += -P$(unisim_dir)
  78
  79 core_tbs = multiply_tb divider_tb rotator_tb countzero_tb
  80 soc_tbs = core_tb icache_tb dcache_tb dmi_dtm_tb wishbone_bram_tb
  81 soc_flash_tbs = core_flash_tb
  82 soc_dram_tbs = dram_tb core_dram_tb
  83
  84 ifneq ($(FLASH_MODEL_PATH),)
  85 fmf_dir = $(FLASH_MODEL_PATH)/fmf
  86 fmf_lib = $(fmf_dir)/fmf-obj08.cf
  87 fmf_lib_files = $(wildcard $(fmf_dir)/*.vhd)
  88 GHDLFLAGS += -P$(fmf_dir)
  89 $(fmf_lib): $(fmf_lib_files)
  90         $(GHDL) -i --std=08 --work=fmf --workdir=$(fmf_dir) $^
  91
  92 flash_model_files=$(FLASH_MODEL_PATH)/s25fl128s.vhd
  93 flash_model_files: $(fmf_lib)
  94 else
  95 flash_model_files=sim_no_flash.vhdl
  96 fmf_lib=
  97 endif
  98
  99 $(soc_flash_tbs): %: $(soc_sim_files) $(soc_sim_obj_files) $(unisim_lib) $(fmf_lib) $(flash_model_files) %.vhdl
 100         $(GHDL) -c $(GHDLFLAGS) $(soc_sim_link) $(soc_sim_files) $(flash_model_files) $@.vhdl $(unisim_files) -e $@
 101
 102 $(soc_tbs): %: $(soc_sim_files) $(soc_sim_obj_files) $(unisim_lib) %.vhdl
 103         $(GHDL) -c $(GHDLFLAGS) $(soc_sim_link) $(soc_sim_files) $@.vhdl -e $@
 104
 105 $(core_tbs): %: $(core_files) glibc_random.vhdl glibc_random_helpers.vhdl %.vhdl
 106         $(GHDL) -c $(GHDLFLAGS) $(core_files) glibc_random.vhdl glibc_random_helpers.vhdl $@.vhdl -e $@
 107
 108 soc_reset_tb: fpga/soc_reset_tb.vhdl fpga/soc_reset.vhdl
 109         $(GHDL) -c $(GHDLFLAGS) fpga/soc_reset_tb.vhdl fpga/soc_reset.vhdl -e $@
 110
 111 # LiteDRAM sim
 112 VERILATOR_ROOT=$(shell verilator -getenv VERILATOR_ROOT 2>/dev/null)
 113 ifeq (, $(VERILATOR_ROOT))
 114 $(soc_dram_tbs):
 115         $(error "Verilator is required to make this target !")
 116 else
 117
 118 VERILATOR_CFLAGS=-O3
 119 VERILATOR_FLAGS=-O3
 120 verilated_dram: litedram/generated/sim/litedram_core.v
 121         verilator $(VERILATOR_FLAGS) -CFLAGS $(VERILATOR_CFLAGS) -Wno-fatal --cc $< --trace
 122         make -C obj_dir -f ../litedram/extras/sim_dram_verilate.mk VERILATOR_ROOT=$(VERILATOR_ROOT)
 123
 124 SIM_DRAM_CFLAGS  = -I. -Iobj_dir -Ilitedram/generated/sim -I$(VERILATOR_ROOT)/include -I$(VERILATOR_ROOT)/include/vltstd
 125 SIM_DRAM_CFLAGS += -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVL_PRINTF=printf -faligned-new
 126 sim_litedram_c.o: litedram/extras/sim_litedram_c.cpp verilated_dram
 127         $(CC)  $(CPPFLAGS) $(SIM_DRAM_CFLAGS) $(CFLAGS) -c $< -o $@
 128
 129 soc_dram_files = $(core_files) $(soc_files) litedram/extras/litedram-wrapper-l2.vhdl litedram/generated/sim/litedram-initmem.vhdl
 130 soc_dram_sim_files = $(soc_sim_files) litedram/extras/sim_litedram.vhdl
 131 soc_dram_sim_obj_files = $(soc_sim_obj_files) sim_litedram_c.o
 132 dram_link_files=-Wl,obj_dir/Vlitedram_core__ALL.a -Wl,obj_dir/verilated.o -Wl,obj_dir/verilated_vcd_c.o -Wl,-lstdc++
 133 soc_dram_sim_link=$(patsubst %,-Wl$(comma)%,$(soc_dram_sim_obj_files)) $(dram_link_files)
 134
 135 $(soc_dram_tbs): %: $(soc_dram_files) $(soc_dram_sim_files) $(soc_dram_sim_obj_files) $(flash_model_files) $(unisim_lib) $(fmf_lib) %.vhdl
 136         $(GHDL) -c $(GHDLFLAGS) $(soc_dram_sim_link) $(soc_dram_files) $(soc_dram_sim_files) $(flash_model_files) $@.vhdl -e $@
 137 endif
 138
 139 # Hello world
 140 MEMORY_SIZE=8192
 141 RAM_INIT_FILE=hello_world/hello_world.hex
 142
 143 # Micropython
 144 #MEMORY_SIZE=393216
 145 #RAM_INIT_FILE=micropython/firmware.hex
 146
 147 FPGA_TARGET ?= ORANGE-CRAB
 148
 149 # OrangeCrab with ECP85
 150 ifeq ($(FPGA_TARGET), ORANGE-CRAB)
 151 RESET_LOW=true
 152 CLK_INPUT=50000000
 153 CLK_FREQUENCY=40000000
 154 LPF=constraints/orange-crab.lpf
 155 PACKAGE=CSFBGA285
 156 NEXTPNR_FLAGS=--um5g-85k --freq 40
 157 OPENOCD_JTAG_CONFIG=openocd/olimex-arm-usb-tiny-h.cfg
 158 OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg
 159 endif
 160
 161 # ECP5-EVN
 162 ifeq ($(FPGA_TARGET), ECP5-EVN)
 163 RESET_LOW=true
 164 CLK_INPUT=12000000
 165 CLK_FREQUENCY=40000000
 166 LPF=constraints/ecp5-evn.lpf
 167 PACKAGE=CABGA381
 168 NEXTPNR_FLAGS=--um5g-85k --freq 40
 169 OPENOCD_JTAG_CONFIG=openocd/ecp5-evn.cfg
 170 OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg
 171 endif
 172
 173 GHDL_IMAGE_GENERICS=-gMEMORY_SIZE=$(MEMORY_SIZE) -gRAM_INIT_FILE=$(RAM_INIT_FILE) \
 174         -gRESET_LOW=$(RESET_LOW) -gCLK_INPUT=$(CLK_INPUT) -gCLK_FREQUENCY=$(CLK_FREQUENCY)
 175
 176 clkgen=fpga/clk_gen_ecp5.vhd
 177 toplevel=fpga/top-generic.vhdl
 178 dmi_dtm=dmi_dtm_dummy.vhdl
 179
 180 ifeq ($(FPGA_TARGET), verilator)
 181 RESET_LOW=true
 182 CLK_INPUT=50000000
 183 CLK_FREQUENCY=50000000
 184 clkgen=fpga/clk_gen_bypass.vhd
 185 endif
 186
 187 fpga_files = fpga/soc_reset.vhdl \
 188         fpga/pp_fifo.vhd fpga/pp_soc_uart.vhd fpga/main_bram.vhdl \
 189         nonrandom.vhdl
 190
 191 synth_files = $(core_files) $(soc_files) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm)
 192
 193 microwatt.json: $(synth_files) $(RAM_INIT_FILE)
 194         $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; synth_ecp5 -json $@  $(SYNTH_ECP5_FLAGS)" $(uart_files)
 195
 196 microwatt.v: $(synth_files) $(RAM_INIT_FILE)
 197         $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; write_verilog $@"
 198
 199 # Need to investigate why yosys is hitting verilator warnings, and eventually turn on -Wall
 200 microwatt-verilator: microwatt.v verilator/microwatt-verilator.cpp verilator/uart-verilator.c
 201         verilator -O3 -CFLAGS "-DCLK_FREQUENCY=$(CLK_FREQUENCY)" --assert --cc microwatt.v --exe verilator/microwatt-verilator.cpp verilator/uart-verilator.c -o $@ -Iuart16550 -Wno-fatal -Wno-CASEOVERLAP -Wno-UNOPTFLAT #--trace
 202         make -C obj_dir -f Vmicrowatt.mk
 203         @cp -f obj_dir/microwatt-verilator microwatt-verilator
 204
 205 microwatt_out.config: microwatt.json $(LPF)
 206         $(NEXTPNR) --json $< --lpf $(LPF) --textcfg $@.tmp $(NEXTPNR_FLAGS) --package $(PACKAGE)
 207         mv -f $@.tmp $@
 208
 209 microwatt.bit: microwatt_out.config
 210         $(ECPPACK) --svf microwatt.svf $< $@
 211
 212 microwatt.svf: microwatt.bit
 213
 214 prog: microwatt.svf
 215         $(OPENOCD) -f $(OPENOCD_JTAG_CONFIG) -f $(OPENOCD_DEVICE_CONFIG) -c "transport select jtag; init; svf $<; exit"
 216
 217 tests = $(sort $(patsubst tests/%.out,%,$(wildcard tests/*.out)))
 218 tests_console = $(sort $(patsubst tests/%.console_out,%,$(wildcard tests/*.console_out)))
 219
 220 tests_console: $(tests_console)
 221
 222 check: $(tests) tests_console test_micropython test_micropython_long tests_unit
 223
 224 check_light: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 test_micropython test_micropython_long tests_console tests_unit
 225
 226 $(tests): core_tb
 227         @./scripts/run_test.sh $@
 228
 229 $(tests_console): core_tb
 230         @./scripts/run_test_console.sh $@
 231
 232 test_micropython: core_tb
 233         @./scripts/test_micropython.py
 234
 235 test_micropython_long: core_tb
 236         @./scripts/test_micropython_long.py
 237
 238 tests_core_tb = $(patsubst %_tb,%_tb_test,$(core_tbs))
 239 tests_soc_tb = $(patsubst %_tb,%_tb_test,$(soc_tbs))
 240
 241 %_test: %
 242         ./$< --assert-level=error > /dev/null
 243
 244 tests_core: $(tests_core_tb)
 245
 246 tests_soc: $(tests_soc_tb)
 247
 248 # FIXME SOC tests have bit rotted, so disable for now
 249 #tests_unit: tests_core tests_soc
 250 tests_unit: tests_core
 251
 252 TAGS:
 253         find . -name '*.vhdl' | xargs ./scripts/vhdltags
 254
 255 .PHONY: TAGS
 256
 257 _clean:
 258         rm -f *.o *.cf $(all)
 259         rm -f fpga/*.o fpga/*.cf
 260         rm -f sim-unisim/*.o sim-unisim/*.cf
 261         rm -f litedram/extras/*.o
 262         rm -f TAGS
 263         rm -f scripts/mw_debug/*.o
 264         rm -f scripts/mw_debug/mw_debug
 265         rm -f microwatt.bin microwatt.json microwatt.svf microwatt_out.config
 266         rm -f microwatt.v microwatt-verilator
 267         rm -rf obj_dir/
 268
 269 clean: _clean
 270         make -f scripts/mw_debug/Makefile clean
 271         make -f hello_world/Makefile clean
 272
 273 distclean: _clean
 274         rm -f *~ fpga/*~ lib/*~ console/*~ include/*~
 275         rm -rf litedram/build
 276         rm -f litedram/extras/*~
 277         rm -f litedram/gen-src/*~
 278         rm -f litedram/gen-src/sdram_init/*~
 279         make -f scripts/mw_debug/Makefile distclean
 280         make -f hello_world/Makefile distclean
 281
 282 .PHONY: all prog check check_light clean distclean
 283 .PRECIOUS: microwatt.json microwatt_out.config microwatt.bit