3 .PHONY
: help Makefile gitupdate
install run_sim
test htmlupload
7 git submodule update
--init
--recursive
--remote
11 cp pinmux
/ls180
/ls180_pins.py src
/soc
/debug
12 cp pinmux
/ls180
/ls180_pins.py src
/soc
/litex
/florent
/libresoc
14 install: gitupdate develop mkpinmux
16 # this is now actually part of openpower-isa repository
18 echo
"pywriter is part of openpower-isa, run that instead"
20 # this is now actually part of openpower-isa repository
22 echo
"sv_analysis is part of openpower-isa, run that instead"
25 python3 setup.py develop
# yes, develop, not install
27 # build and run libresoc litex simulation
29 python3 src
/soc
/simple
/issuer_verilog.py
--disable-svp64 \
30 src
/soc
/litex
/florent
/libresoc
/libresoc.v
31 python3 src
/soc
/litex
/florent
/sim.py
--cpu
=libresoc
33 # and with test gpio (useful for XICS IRC testing)
35 python3 src
/soc
/simple
/issuer_verilog.py \
36 src
/soc
/litex
/florent
/libresoc
/libresoc.v \
38 python3 src
/soc
/litex
/florent
/sim.py
--cpu
=libresoc \
39 --variant
=standardjtagtestgpio
42 python3 src
/soc
/simple
/issuer_verilog.py \
43 --debug
=jtag
--enable-core
--disable-pll \
44 --enable-xics
--disable-svp64 \
45 src
/soc
/litex
/florent
/libresoc
/libresoc.v
48 python3 src
/soc
/simple
/issuer_verilog.py \
49 --debug
=jtag
--enable-core
--enable-pll \
50 --enable-xics
--disable-svp64 \
51 src
/soc
/litex
/florent
/libresoc
/libresoc.v
54 python3 src
/soc
/simple
/issuer_verilog.py \
55 --debug
=jtag
--enable-core
--enable-pll \
56 --enable-xics
--enable-sram4x4kblock
--disable-svp64 \
57 src
/soc
/litex
/florent
/libresoc
/libresoc.v
59 # build microwatt "external core", note that the TLB set size is set to 16
60 # for I/D-Cache which needs a corresponding alteration of the device-tree
62 microwatt_external_core
:
63 python3 src
/soc
/simple
/issuer_verilog.py
--microwatt-compat
--enable-mmu \
66 microwatt_external_core_spi
:
67 python3 src
/soc
/simple
/issuer_verilog.py
--microwatt-compat \
70 --pc-reset
0x10000000 \
73 # microwatt-compatible core with smaller cache size (quick. VERSA_ECP5. just)
74 microwatt_external_core_bram
:
75 python3 src
/soc
/simple
/issuer_verilog.py
--microwatt-compat \
78 --pc-reset
0xFF000000 \
81 # microwatt-compatible core with larger cache size (experiment on arty)
82 microwatt_external_core_bram_arty
:
83 python3 src
/soc
/simple
/issuer_verilog.py
--microwatt-compat \
85 --pc-reset
0xFF000000 \
88 # build the litex libresoc SoC without 4k SRAMs
89 ls180_verilog_build
: ls180_verilog
90 make
-C soc
/soc
/litex
/florent ls180
92 # build the litex libresoc SoC with 4k SRAMs
93 ls180_4ksram_verilog_build
: ls180_4k_verilog
94 make
-C soc
/soc
/litex
/florent ls1804k
96 # testing (usually done at install time)
98 python3 setup.py
test # could just run nosetest3...
101 $(PYTHON3
) setup.py sdist upload
103 # Minimal makefile for Sphinx documentation
106 # You can set these variables from the command line.
108 SPHINXBUILD
= sphinx-build
109 SPHINXPROJ
= Libre-SOC
113 # Put it first so that "make" without argument is like "make help".
115 @
$(SPHINXBUILD
) -M help
"$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS
) $(O
)
117 # copies all documentation to libre-soc (libre-soc admins only)
118 htmlupload
: clean html
119 rsync
-HPavz
--delete build
/html
/* \
120 libre-soc.org
:/var
/www
/libre-soc.org
/docs
/soc
/
122 # Catch-all target: route all unknown targets to Sphinx using the new
123 # "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS).
125 echo
"catch-all falling through to sphinx for document building"
126 mkdir
-p
"$(SOURCEDIR)"/src
/gen
127 sphinx-apidoc
--ext-autodoc
-o
"$(SOURCEDIR)"/src
/gen .
/src
/soc
128 @
$(SPHINXBUILD
) -M
$@
"$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS
) $(O
)