434bcda34c04791ad4408734af93c45fdd43d12f
2 .
/ls180soc.py
--build
--platform
=ls180
3 cp build
/ls180
/gateware
/ls180.v .
4 cp build
/ls180
/gateware
/mem.init .
5 cp build
/ls180
/gateware
/mem_1.init .
6 cp build
/ls180
/gateware
/mem_2.init .
7 cp build
/ls180
/gateware
/mem_3.init .
8 cp build
/ls180
/gateware
/mem_4.init .
9 cp libresoc
/libresoc.v .
10 yosys
-p
'read_verilog libresoc.v' \
11 -p
'write_ilang libresoc_cvt.il'
12 yosys
-p
'read_verilog ls180.v' \
13 -p
'read_verilog SPBlock_512W64B8W.v' \
14 -p
'write_ilang ls180_cvt.il'
15 yosys
-p
'read_ilang ls180_cvt.il' \
16 -p
'read_ilang libresoc_cvt.il' \
17 -p
'write_ilang ls180.il'
20 .
/versa_ecp5.py
--sys-clk-freq
=55e6
--build
23 .
/versa_ecp5.py
--sys-clk-freq
=55e6
--load