Makefile

   1 GHDL ?= ghdl
   2 GHDLFLAGS=--std=08 -frelaxed
   3 CFLAGS=-O3 -Wall
   4
   5 ifeq ($(shell uname -m),ppc64le)
   6 CFLAG_ARCH_OPT=-mcpu=native
   7 else
   8 CFLAG_ARCH_OPT=-march=native
   9 endif
  10
  11 CFLAGS=-O3 -Wall $(CFLAG_ARCH_OPT) -mtune=native
  12 CXXFLAGS=-g -g
  13
  14 # Use this for parallel builds
  15 JOBS= $(shell nproc)
  16
  17 GHDLSYNTH ?= ghdl.so
  18 YOSYS     ?= yosys
  19 NEXTPNR   ?= nextpnr-ecp5
  20 ECPPACK   ?= ecppack
  21 OPENOCD   ?= openocd
  22
  23 # We need a version of GHDL built with either the LLVM or gcc backend.
  24 # Fedora provides this, but other distros may not. Another option is to use
  25 # the Docker image.
  26 DOCKER ?= 0
  27 PODMAN ?= 0
  28
  29 ifeq ($(DOCKER), 1)
  30 DOCKERBIN=docker
  31 USE_DOCKER=1
  32 endif
  33
  34 ifeq ($(PODMAN), 1)
  35 DOCKERBIN=podman
  36 USE_DOCKER=1
  37 endif
  38
  39 ifeq ($(USE_DOCKER), 1)
  40 PWD = $(shell pwd)
  41 DOCKERARGS = run --rm -v $(PWD):/src:z -w /src
  42 GHDL      = $(DOCKERBIN) $(DOCKERARGS) ghdl/ghdl:buster-llvm-7 ghdl
  43 CC        = $(DOCKERBIN) $(DOCKERARGS) ghdl/ghdl:buster-llvm-7 gcc
  44 GHDLSYNTH = ghdl
  45 YOSYS     = $(DOCKERBIN) $(DOCKERARGS) hdlc/ghdl:yosys yosys
  46 NEXTPNR   = $(DOCKERBIN) $(DOCKERARGS) hdlc/nextpnr:ecp5 nextpnr-ecp5
  47 ECPPACK   = $(DOCKERBIN) $(DOCKERARGS) hdlc/prjtrellis ecppack
  48 OPENOCD   = $(DOCKERBIN) $(DOCKERARGS) --device /dev/bus/usb hdlc/prog openocd
  49 endif
  50
  51 all = core_tb icache_tb dcache_tb multiply_tb dmi_dtm_tb divider_tb \
  52         rotator_tb countzero_tb wishbone_bram_tb soc_reset_tb
  53
  54 all: $(all)
  55
  56 core_files = decode_types.vhdl common.vhdl wishbone_types.vhdl fetch1.vhdl \
  57         utils.vhdl plru.vhdl cache_ram.vhdl icache.vhdl \
  58         decode1.vhdl helpers.vhdl insn_helpers.vhdl \
  59         control.vhdl decode2.vhdl register_file.vhdl \
  60         cr_file.vhdl crhelpers.vhdl ppc_fx_insns.vhdl rotator.vhdl \
  61         logical.vhdl countzero.vhdl multiply.vhdl divider.vhdl execute1.vhdl \
  62         loadstore1.vhdl mmu.vhdl dcache.vhdl writeback.vhdl core_debug.vhdl \
  63         core.vhdl fpu.vhdl
  64
  65 _soc_files = wishbone_arbiter.vhdl wishbone_bram_wrapper.vhdl sync_fifo.vhdl \
  66         wishbone_debug_master.vhdl xics.vhdl syscon.vhdl soc.vhdl \
  67         spi_rxtx.vhdl spi_flash_ctrl.vhdl
  68
  69 soc_files = $(core_files) $(_soc_files)
  70
  71 uart_files = $(wildcard uart16550/*.v)
  72
  73 soc_sim_files = $(soc_files) sim_console.vhdl sim_pp_uart.vhdl sim_bram_helpers.vhdl \
  74         sim_bram.vhdl sim_jtag_socket.vhdl sim_jtag.vhdl dmi_dtm_xilinx.vhdl \
  75         sim_16550_uart.vhdl \
  76         random.vhdl glibc_random.vhdl glibc_random_helpers.vhdl
  77
  78 soc_sim_c_files = sim_vhpi_c.c sim_bram_helpers_c.c sim_console_c.c \
  79         sim_jtag_socket_c.c
  80
  81 soc_sim_obj_files=$(soc_sim_c_files:.c=.o)
  82 comma := ,
  83 soc_sim_link=$(patsubst %,-Wl$(comma)%,$(soc_sim_obj_files))
  84
  85 unisim_dir = sim-unisim
  86 unisim_lib = $(unisim_dir)/unisim-obj08.cf
  87 unisim_lib_files = $(unisim_dir)/BSCANE2.vhdl $(unisim_dir)/BUFG.vhdl \
  88         $(unisim_dir)/unisim_vcomponents.vhdl
  89 $(unisim_lib): $(unisim_lib_files)
  90         $(GHDL) -i --std=08 --work=unisim --workdir=$(unisim_dir) $^
  91 GHDLFLAGS += -P$(unisim_dir)
  92
  93 core_tbs = multiply_tb divider_tb rotator_tb countzero_tb
  94 soc_tbs = core_tb icache_tb dcache_tb dmi_dtm_tb wishbone_bram_tb
  95 soc_flash_tbs = core_flash_tb
  96 soc_dram_tbs = dram_tb core_dram_tb
  97
  98 ifneq ($(FLASH_MODEL_PATH),)
  99 fmf_dir = $(FLASH_MODEL_PATH)/fmf
 100 fmf_lib = $(fmf_dir)/fmf-obj08.cf
 101 fmf_lib_files = $(wildcard $(fmf_dir)/*.vhd)
 102 GHDLFLAGS += -P$(fmf_dir)
 103 $(fmf_lib): $(fmf_lib_files)
 104         $(GHDL) -i --std=08 --work=fmf --workdir=$(fmf_dir) $^
 105
 106 flash_model_files=$(FLASH_MODEL_PATH)/s25fl128s.vhd
 107 flash_model_files: $(fmf_lib)
 108 else
 109 flash_model_files=sim_no_flash.vhdl
 110 fmf_lib=
 111 endif
 112
 113 $(soc_flash_tbs): %: $(soc_sim_files) $(soc_sim_obj_files) $(unisim_lib) $(fmf_lib) $(flash_model_files) %.vhdl
 114         $(GHDL) -c $(GHDLFLAGS) $(soc_sim_link) $(soc_sim_files) $(flash_model_files) $@.vhdl $(unisim_files) -e $@
 115
 116 $(soc_tbs): %: $(soc_sim_files) $(soc_sim_obj_files) $(unisim_lib) %.vhdl
 117         $(GHDL) -c $(GHDLFLAGS) $(soc_sim_link) $(soc_sim_files) $@.vhdl -e $@
 118
 119 $(core_tbs): %: $(core_files) glibc_random.vhdl glibc_random_helpers.vhdl %.vhdl
 120         $(GHDL) -c $(GHDLFLAGS) $(core_files) glibc_random.vhdl glibc_random_helpers.vhdl $@.vhdl -e $@
 121
 122 soc_reset_tb: fpga/soc_reset_tb.vhdl fpga/soc_reset.vhdl
 123         $(GHDL) -c $(GHDLFLAGS) fpga/soc_reset_tb.vhdl fpga/soc_reset.vhdl -e $@
 124
 125 # LiteDRAM sim
 126 VERILATOR_ROOT=$(shell verilator -getenv VERILATOR_ROOT 2>/dev/null)
 127 ifeq (, $(VERILATOR_ROOT))
 128 $(soc_dram_tbs):
 129         $(error "Verilator is required to make this target !")
 130 else
 131
 132 VERILATOR_CFLAGS=-O3
 133 VERILATOR_FLAGS=-O3
 134 verilated_dram: litedram/generated/sim/litedram_core.v
 135         verilator $(VERILATOR_FLAGS) -CFLAGS $(VERILATOR_CFLAGS) -Wno-fatal --cc $< --trace
 136         make -C obj_dir -f ../litedram/extras/sim_dram_verilate.mk VERILATOR_ROOT=$(VERILATOR_ROOT)
 137
 138 SIM_DRAM_CFLAGS  = -I. -Iobj_dir -Ilitedram/generated/sim -I$(VERILATOR_ROOT)/include -I$(VERILATOR_ROOT)/include/vltstd
 139 SIM_DRAM_CFLAGS += -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVL_PRINTF=printf -faligned-new
 140 sim_litedram_c.o: litedram/extras/sim_litedram_c.cpp verilated_dram
 141         $(CC)  $(CPPFLAGS) $(SIM_DRAM_CFLAGS) $(CFLAGS) -c $< -o $@
 142
 143 soc_dram_files = $(soc_files) litedram/extras/litedram-wrapper-l2.vhdl litedram/generated/sim/litedram-initmem.vhdl
 144 soc_dram_sim_files = $(soc_sim_files) litedram/extras/sim_litedram.vhdl
 145 soc_dram_sim_obj_files = $(soc_sim_obj_files) sim_litedram_c.o
 146 dram_link_files=-Wl,obj_dir/Vlitedram_core__ALL.a -Wl,obj_dir/verilated.o -Wl,obj_dir/verilated_vcd_c.o -Wl,-lstdc++
 147 soc_dram_sim_link=$(patsubst %,-Wl$(comma)%,$(soc_dram_sim_obj_files)) $(dram_link_files)
 148
 149 $(soc_dram_tbs): %: $(soc_dram_files) $(soc_dram_sim_files) $(soc_dram_sim_obj_files) $(flash_model_files) $(unisim_lib) $(fmf_lib) %.vhdl
 150         $(GHDL) -c $(GHDLFLAGS) $(soc_dram_sim_link) $(soc_dram_files) $(soc_dram_sim_files) $(flash_model_files) $@.vhdl -e $@
 151 endif
 152
 153 # Hello world
 154 MEMORY_SIZE=8192
 155 RAM_INIT_FILE=hello_world/hello_world.hex
 156 SIM_MAIN_BRAM=false
 157
 158 # Micropython
 159 #MEMORY_SIZE=393216
 160 #RAM_INIT_FILE=micropython/firmware.hex
 161
 162 # Linux
 163 #MEMORY_SIZE=536870912
 164 #RAM_INIT_FILE=dtbImage.microwatt.hex
 165 #SIM_MAIN_BRAM=false
 166 SIM_BRAM_CHAINBOOT=6291456 # 0x600000
 167
 168 FPGA_TARGET ?= ORANGE-CRAB
 169
 170 clkgen=fpga/clk_gen_ecp5.vhd
 171 toplevel=fpga/top-generic.vhdl
 172 dmi_dtm=dmi_dtm_dummy.vhdl
 173
 174 # ULX3S with ECP85
 175 ifeq ($(FPGA_TARGET), ULX3S)
 176 RESET_LOW=true
 177 CLK_INPUT=25000000
 178 CLK_FREQUENCY=12500000
 179 LPF=constraints/ulx3s.lpf
 180 PACKAGE=CABGA381
 181 NEXTPNR_FLAGS=--85k --freq 25
 182 OPENOCD_JTAG_CONFIG=openocd/ulx3s.cfg
 183 OPENOCD_DEVICE_CONFIG=openocd/LFE5U-85F.cfg
 184 toplevel=fpga/top-ulx3s.vhdl
 185 endif
 186
 187 # OrangeCrab with ECP85
 188 ifeq ($(FPGA_TARGET), ORANGE-CRAB)
 189 RESET_LOW=true
 190 CLK_INPUT=50000000
 191 CLK_FREQUENCY=40000000
 192 LPF=constraints/orange-crab.lpf
 193 PACKAGE=CSFBGA285
 194 NEXTPNR_FLAGS=--um5g-85k --freq 40
 195 OPENOCD_JTAG_CONFIG=openocd/olimex-arm-usb-tiny-h.cfg
 196 OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg
 197 endif
 198
 199 # ECP5-EVN
 200 ifeq ($(FPGA_TARGET), ECP5-EVN)
 201 RESET_LOW=true
 202 CLK_INPUT=12000000
 203 CLK_FREQUENCY=40000000
 204 LPF=constraints/ecp5-evn.lpf
 205 PACKAGE=CABGA381
 206 NEXTPNR_FLAGS=--um5g-85k --freq 40
 207 OPENOCD_JTAG_CONFIG=openocd/ecp5-evn.cfg
 208 OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg
 209 endif
 210
 211
 212
 213 ifeq ($(FPGA_TARGET), verilator)
 214 RESET_LOW=true
 215 CLK_INPUT=50000000
 216 CLK_FREQUENCY=50000000
 217 clkgen=fpga/clk_gen_bypass.vhd
 218 endif
 219
 220 FPGA_MAIN_BRAM=fpga/main_bram.vhdl
 221 #FPGA_MAIN_BRAM=
 222
 223 _fpga_files = fpga/soc_reset.vhdl \
 224         fpga/pp_fifo.vhd fpga/pp_soc_uart.vhd $(FPGA_MAIN_BRAM) \
 225         nonrandom.vhdl
 226
 227 # use an alternative core (in verilog)
 228 EXTERNAL_CORE=false
 229 # VHDL does not allow integers greater than 2^32, so shift down
 230 # by 16 bits and add 16 bits zeros back on in soc-generic.vhdl
 231 RESET_ADDRESS=0 # 65280 # 0xff00_0000>>16
 232 ifeq ($(EXTERNAL_CORE),false)
 233     fpga_files = $(_fpga_files) $(_soc_files) $(core_files)
 234     synth_files = $(core_files) $(soc_files) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm)
 235 else
 236     util_files = decode_types.vhdl common.vhdl wishbone_types.vhdl utils.vhdl \
 237                 core_dummy.vhdl
 238     fpga_files = $(_fpga_files) $(_soc_files)
 239     synth_files = $(util_files) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm)
 240     soc_extra_v = external_core_top.v
 241 endif
 242
 243 GHDL_IMAGE_GENERICS=-gMEMORY_SIZE=$(MEMORY_SIZE) \
 244     -gRAM_INIT_FILE=$(RAM_INIT_FILE) \
 245         -gRESET_LOW=$(RESET_LOW) \
 246         -gRESET_ADDRESS=$(RESET_ADDRESS) \
 247     -gCLK_INPUT=$(CLK_INPUT) \
 248     -gCLK_FREQUENCY=$(CLK_FREQUENCY) \
 249         -gSIM_MAIN_BRAM=$(SIM_MAIN_BRAM) \
 250     -gSIM_BRAM_CHAINBOOT=$(SIM_BRAM_CHAINBOOT) \
 251         -gEXTERNAL_CORE=$(EXTERNAL_CORE)
 252
 253 microwatt.json: $(synth_files) $(RAM_INIT_FILE)
 254         $(YOSYS) -m $(GHDLSYNTH) -p \
 255                 "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) \
 256                 $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; \
 257                 read_verilog $(uart_files) $(soc_extra_v); \
 258                 synth_ecp5 -top toplevel -nowidelut -json $@  $(SYNTH_ECP5_FLAGS)"
 259
 260 microwatt.v: $(synth_files) $(RAM_INIT_FILE)
 261         $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; write_verilog $@"
 262
 263 THREADS=3 # How many threads should be used for verilator binary, 3 is optimal
 264 # Need to investigate why yosys is hitting verilator warnings, and eventually turn on -Wall
 265 # --top-module toplevel
 266 microwatt-verilator: microwatt.v verilator/microwatt-verilator.cpp verilator/uart-verilator.c
 267         verilator -O3 -CFLAGS "-DCLK_FREQUENCY=$(CLK_FREQUENCY) -I../verilator" \
 268     --threads $(THREADS) \
 269     --assert \
 270     --cc microwatt.v \
 271     --exe verilator/microwatt-verilator.cpp verilator/uart-verilator.c \
 272     -o $@ -Iuart16550 \
 273         -Wno-fatal -Wno-CASEOVERLAP -Wno-UNOPTFLAT \
 274             -Wno-BLKANDNBLK \
 275             -Wno-COMBDLY  \
 276             -Wno-CASEINCOMPLETE \
 277             -Wno-WIDTH \
 278          --savable \
 279          --trace \
 280          --threads-dpi all --x-initial fast \
 281          -CFLAGS $(CFLAG_ARCH_OPT) \
 282          -CFLAGS -mtune=native \
 283          -CFLAGS -O3 \
 284         # -CFLAGS -flto #disabled for now, no measured performance benefit \
 285         #    --unroll-count 256 \
 286         #    --output-split 5000 \
 287         #    --output-split-cfuncs 500 \
 288         #    --output-split-ctrace 500
 289         make -j $(JOBS) -C obj_dir -f Vmicrowatt.mk
 290         @cp -f obj_dir/microwatt-verilator microwatt-verilator
 291
 292 microwatt_out.config: microwatt.json $(LPF)
 293         $(NEXTPNR) --json $< --lpf $(LPF) --lpf-allow-unconstrained \
 294                     --textcfg $@.tmp $(NEXTPNR_FLAGS) --package $(PACKAGE)
 295         mv -f $@.tmp $@
 296
 297 microwatt.bit: microwatt_out.config
 298         $(ECPPACK) --svf microwatt.svf $< $@
 299
 300 microwatt.svf: microwatt.bit
 301
 302 prog: microwatt.svf
 303         $(OPENOCD) -f $(OPENOCD_JTAG_CONFIG) -f $(OPENOCD_DEVICE_CONFIG) -c "transport select jtag; init; svf $<; exit"
 304
 305 tests = $(sort $(patsubst tests/%.out,%,$(wildcard tests/*.out)))
 306 tests_console = $(sort $(patsubst tests/%.console_out,%,$(wildcard tests/*.console_out)))
 307
 308 tests_console: $(tests_console)
 309
 310 check: $(tests) tests_console test_micropython test_micropython_long tests_unit
 311
 312 check_light: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 test_micropython test_micropython_long tests_console tests_unit
 313
 314 $(tests): core_tb
 315         @./scripts/run_test.sh $@
 316
 317 $(tests_console): core_tb
 318         @./scripts/run_test_console.sh $@
 319
 320 test_micropython: core_tb
 321         @./scripts/test_micropython.py
 322
 323 test_micropython_long: core_tb
 324         @./scripts/test_micropython_long.py
 325
 326 tests_core_tb = $(patsubst %_tb,%_tb_test,$(core_tbs))
 327 tests_soc_tb = $(patsubst %_tb,%_tb_test,$(soc_tbs))
 328
 329 %_test: %
 330         ./$< --assert-level=error > /dev/null
 331
 332 tests_core: $(tests_core_tb)
 333
 334 tests_soc: $(tests_soc_tb)
 335
 336 # FIXME SOC tests have bit rotted, so disable for now
 337 #tests_unit: tests_core tests_soc
 338 tests_unit: tests_core
 339
 340 TAGS:
 341         find . -name '*.vhdl' | xargs ./scripts/vhdltags
 342
 343 .PHONY: TAGS
 344
 345 _clean:
 346         rm -f *.o *.cf $(all)
 347         rm -f fpga/*.o fpga/*.cf
 348         rm -f sim-unisim/*.o sim-unisim/*.cf
 349         rm -f litedram/extras/*.o
 350         rm -f TAGS
 351         rm -f scripts/mw_debug/*.o
 352         rm -f scripts/mw_debug/mw_debug
 353         rm -f microwatt.bin microwatt.json microwatt.svf microwatt_out.config
 354         rm -f microwatt.v microwatt-verilator
 355         rm -rf obj_dir/
 356
 357 clean: _clean
 358         make -f scripts/mw_debug/Makefile clean
 359         make -f hello_world/Makefile clean
 360
 361 distclean: _clean
 362         rm -f *~ fpga/*~ lib/*~ console/*~ include/*~
 363         rm -rf litedram/build
 364         rm -f litedram/extras/*~
 365         rm -f litedram/gen-src/*~
 366         rm -f litedram/gen-src/sdram_init/*~
 367         make -f scripts/mw_debug/Makefile distclean
 368         make -f hello_world/Makefile distclean
 369
 370 .PHONY: all prog check check_light clean distclean
 371 .PRECIOUS: microwatt.json microwatt_out.config microwatt.bit