a56d541363fd1f9cb1f678dbaa961b2e93b28205
2 .
/ls180soc.py
--build
--platform
=ls180sram4k
--num-srams
=2
3 cp build
/ls180
/gateware
/ls180.v .
4 cp build
/ls180
/gateware
/mem.init .
5 cp build
/ls180
/gateware
/mem_1.init .
6 cp build
/ls180
/gateware
/mem_2.init .
7 cp build
/ls180
/gateware
/mem_3.init .
8 cp build
/ls180
/gateware
/mem_4.init .
9 cp libresoc
/libresoc.v .
10 yosys
-p
'read_verilog libresoc.v' \
11 -p
'write_ilang libresoc_cvt.il'
12 yosys
-p
'read_verilog ls180.v' \
13 -p
'read_verilog SPBlock_512W64B8W.v' \
14 -p
'write_ilang ls180_cvt.il'
15 yosys
-p
'read_ilang ls180_cvt.il' \
16 -p
'read_ilang libresoc_cvt.il' \
17 -p
'write_ilang ls180.il'
20 .
/ls180soc.py
--build
--platform
=ls180
--num-srams
=2
21 cp build
/ls180
/gateware
/ls180.v .
22 cp build
/ls180
/gateware
/mem.init .
23 cp build
/ls180
/gateware
/mem_1.init .
24 cp build
/ls180
/gateware
/mem_2.init .
25 cp build
/ls180
/gateware
/mem_3.init .
26 cp build
/ls180
/gateware
/mem_4.init .
27 cp libresoc
/libresoc.v .
28 yosys
-p
'read_verilog libresoc.v' \
29 -p
'read_verilog ls180.v' \
30 -p
'write_verilog ls180_cvt.v'
31 yosys
-p
'read_verilog ls180.v' \
32 -p
'read_verilog SPBlock_512W64B8W.v' \
33 -p
'write_ilang ls180_cvt.il'
34 yosys
-p
'read_verilog libresoc.v' \
35 -p
'write_ilang libresoc_cvt.il'
36 yosys
-p
'read_verilog ls180.v' \
37 -p
'read_verilog SPBlock_512W64B8W.v' \
38 -p
'write_ilang ls180_cvt.il'
39 yosys
-p
'read_ilang ls180_cvt.il' \
40 -p
'read_ilang libresoc_cvt.il' \
41 -p
'write_ilang ls180.il'
44 .
/versa_ecp5.py
--sys-clk-freq
=55e6
--build
47 .
/versa_ecp5.py
--sys-clk-freq
=55e6
--load