bd7734ec5b93f87c497be5954c1de51a7ef19f48
2 .
/ls180soc.py
--build
--platform
=ls180sram4k
--num-srams
=2
3 cp build
/ls180sram4k
/gateware
/ls180sram4k.v .
/ls180.v
4 cp build
/ls180sram4k
/gateware
/mem.init .
5 cp build
/ls180sram4k
/gateware
/mem_1.init .
6 cp libresoc
/libresoc.v .
7 yosys
-p
'read_verilog libresoc.v' \
8 -p
'write_ilang libresoc_cvt.il'
9 yosys
-p
'read_verilog ls180.v' \
10 -p
'read_verilog SPBlock_512W64B8W.v' \
11 -p
'write_ilang ls180_cvt.il'
12 yosys
-p
'read_ilang ls180_cvt.il' \
13 -p
'read_ilang libresoc_cvt.il' \
14 -p
'write_ilang ls180.il'
17 .
/ls180soc.py
--build
--platform
=ls180
--num-srams
=2
18 cp build
/ls180
/gateware
/ls180.v .
19 cp build
/ls180
/gateware
/mem.init .
20 cp build
/ls180
/gateware
/mem_1.init .
21 cp build
/ls180
/gateware
/mem_2.init .
22 cp build
/ls180
/gateware
/mem_3.init .
23 cp build
/ls180
/gateware
/mem_4.init .
24 cp libresoc
/libresoc.v .
25 yosys
-p
'read_verilog libresoc.v' \
26 -p
'read_verilog ls180.v' \
27 -p
'write_verilog ls180_cvt.v'
28 yosys
-p
'read_verilog ls180.v' \
29 -p
'read_verilog SPBlock_512W64B8W.v' \
30 -p
'write_ilang ls180_cvt.il'
31 yosys
-p
'read_verilog libresoc.v' \
32 -p
'write_ilang libresoc_cvt.il'
33 yosys
-p
'read_verilog ls180.v' \
34 -p
'read_verilog SPBlock_512W64B8W.v' \
35 -p
'write_ilang ls180_cvt.il'
36 yosys
-p
'read_ilang ls180_cvt.il' \
37 -p
'read_ilang libresoc_cvt.il' \
38 -p
'write_ilang ls180.il'
41 .
/versa_ecp5.py
--sys-clk-freq
=55e6
--build
44 .
/versa_ecp5.py
--sys-clk-freq
=55e6
--load