1 # A framework for building SoCs with nMigen
3 **LambdaSoC is a work in progress. Please keep in mind that some interfaces will undergo breaking changes as they evolve and/or get moved [upstream][nmigen-soc].**
8 git clone https://github.com/lambdaconcept/lambdasoc
9 git submodule update --init --recursive
11 pip install -r requirements.txt
12 python setup.py install
17 Let's build and run the SoC example at [examples/sram_soc.py][sram_soc]. It is composed of a [Minerva][minerva] CPU, SRAM storage, an UART and a timer.
20 * A `riscv64-unknown-elf` GNU toolchain, to build the first-stage bootloader
21 * A [supported platform][nmigen-boards] with enough resources to fit the SoC
23 Here, we build the SoC for the `nmigen_boards.arty_a7.ArtyA7Platform`:
25 python examples/sram_soc.py --baudrate=9600 nmigen_boards.arty_a7.ArtyA7Platform
28 The bootloader shell can be accessed from the serial port:
30 flterm --speed=9600 /dev/ttyUSB1
33 (c) Copyright 2007-2020 M-Labs Limited
34 (c) Copyright 2020 LambdaConcept
35 Built Mar 26 2020 13:41:04
37 BIOS CRC passed (c402e7e2)
41 The `help` command lists available commands.
45 LambdaSoC is released under the permissive two-clause BSD license. See LICENSE file for full copyright and license information.
47 [nmigen-soc]: https://github.com/nmigen/nmigen-soc
48 [minerva]: https://github.com/lambdaconcept/minerva
49 [nmigen-boards]: https://github.com/nmigen/nmigen-boards
50 [sram_soc]: https://github.com/lambdaconcept/lambdasoc/blob/master/examples/sram_soc.py