README.md

   1 # A framework for building SoCs with nMigen
   2
   3 **LambdaSoC is a work in progress. Please keep in mind that some interfaces will undergo breaking changes as they evolve and/or get moved [upstream][nmigen-soc].**
   4
   5 ## Installation
   6
   7 ```
   8 git clone https://github.com/lambdaconcept/lambdasoc
   9 git submodule update --init --recursive
  10
  11 pip install git+https://github.com/nmigen/nmigen-soc
  12 pip install git+https://github.com/nmigen/nmigen-stdio
  13 pip install git+https://github.com/nmigen/nmigen-boards
  14 pip install git+https://github.com/lambdaconcept/minerva
  15 pip install git+https://github.com/m-labs/asyncserial
  16
  17 python setup.py install
  18 ```
  19
  20 ## Quick start
  21
  22 Let's build and run the SoC example at [examples/sram_soc.py][sram_soc]. It is composed of a [Minerva][minerva] CPU, SRAM storage, an UART and a timer.
  23
  24 ##### Requirements
  25 * A `riscv64-unknown-elf` GNU toolchain, to build the first-stage bootloader
  26 * A [supported platform][nmigen-boards] with enough resources to fit the SoC
  27
  28 Here, we build the SoC for the `nmigen_boards.arty_a7.ArtyA7Platform`:
  29 ```
  30 python examples/sram_soc.py --baudrate=9600 nmigen_boards.arty_a7.ArtyA7Platform
  31 ```
  32
  33 The bootloader shell can be accessed from the serial port:
  34 ```
  35 flterm --speed=9600 /dev/ttyUSB1
  36
  37 LambdaSoC BIOS
  38 (c) Copyright 2007-2020 M-Labs Limited
  39 (c) Copyright 2020 LambdaConcept
  40 Built Mar 26 2020 13:41:04
  41
  42 BIOS CRC passed (c402e7e2)
  43 BIOS>
  44 ```
  45
  46 The `help` command lists available commands.
  47
  48 ## License
  49
  50 LambdaSoC is released under the permissive two-clause BSD license. See LICENSE file for full copyright and license information.
  51
  52 [nmigen-soc]: https://github.com/nmigen/nmigen-soc
  53 [minerva]: https://github.com/lambdaconcept/minerva
  54 [nmigen-boards]: https://github.com/nmigen/nmigen-boards
  55 [sram_soc]: https://github.com/lambdaconcept/lambdasoc/blob/master/examples/sram_soc.py