README.md

   1 ```
   2                        __   _ __      _  __
   3                       / /  (_) /____ | |/_/
   4                      / /__/ / __/ -_)>  <
   5                     /____/_/\__/\__/_/|_|
   6                   Build your hardware, easily!
   7
   8               Copyright 2012-2019 / EnjoyDigital
   9 ```
  10 [![](https://travis-ci.com/enjoy-digital/litex.svg?branch=master)](https://travis-ci.com/enjoy-digital/litex)
  11 ![License](https://img.shields.io/badge/License-BSD%202--Clause-orange.svg)
  12 # Welcome to LiteX!
  13 LiteX is a FPGA design/SoC builder that can be used to build cores, create
  14 SoCs and full FPGA designs.
  15
  16 LiteX is based on Migen and provides specific building/debugging tools for
  17 a higher level of abstraction and compatibily with the LiteX core ecosystem.
  18
  19 Think of Migen as a toolbox to create FPGA designs in Python and LiteX as a
  20 SoC builder to create/develop/debug FPGA SoCs in Python.
  21
  22 # Typical LiteX design flow:
  23 ```
  24                         +---------------+
  25                         |FPGA toolchains|
  26                         +----^-----+----+
  27                              |     |
  28                           +--+-----v--+
  29          +-------+        |           |
  30          | Migen +-------->           |
  31          +-------+        |           |        Your design
  32                           |   LiteX   +---> ready to be used!
  33                           |           |
  34 +----------------------+  |           |
  35 |LiteX Cores Ecosystem +-->           |
  36 +----------------------+  +-^-------^-+
  37  (Eth, SATA, DRAM, USB,     |       |
  38   PCIe, Video, etc...)      +       +
  39                            board   target
  40                            file    file
  41 ```
  42 LiteX already supports various softcores CPUs: LM32, Mor1kx, PicoRV32, VexRiscv
  43 and is compatible with the LiteX's Cores Ecosystem:
  44
  45 | Name                                                         | Build Status                                                            | Description                   |
  46 | ------------------------------------------------------------ | ----------------------------------------------------------------------- | ----------------------------- |
  47 | [LiteDRAM](http://github.com/enjoy-digital/litedram)         | [![](https://travis-ci.org/enjoy-digital/litedram.svg?branch=master)](https://travis-ci.org/enjoy-digital/litedram)     | DRAM        |
  48 | [LiteEth](http://github.com/enjoy-digital/liteeth)           | [![](https://travis-ci.com/enjoy-digital/liteeth.svg?branch=master)](https://travis-ci.com/enjoy-digital/liteeth)       | Ethernet                      |
  49 | [LitePCIe](http://github.com/enjoy-digital/litepcie)         | [![](https://travis-ci.com/enjoy-digital/litepcie.svg?branch=master)](https://travis-ci.com/enjoy-digital/litpcie)     | PCIe                          |
  50 | [LiteSATA](http://github.com/enjoy-digital/litesata)         | [![](https://travis-ci.com/enjoy-digital/litesata.svg?branch=master)](https://travis-ci.com/enjoy-digital/litesata)     | SATA                          |
  51 | [LiteSDCard](http://github.com/enjoy-digital/litesdcard)     | [![](https://travis-ci.com/enjoy-digital/litesdcard.svg?branch=master)](https://travis-ci.com/enjoy-digital/litesdcard)   | SD card                       |
  52 | [LiteICLink](http://github.com/enjoy-digital/liteiclink)     | [![](https://travis-ci.com/enjoy-digital/liteiclink.svg?branch=master)](https://travis-ci.com/enjoy-digital/liteiclink)   | Inter-Chip communication      |
  53 | [LiteJESD204B](http://github.com/enjoy-digital/litejesd204b) | [![](https://travis-ci.com/enjoy-digital/litejesd204b.svg?branch=master)](https://travis-ci.com/enjoy-digital/litejesd204b) | JESD204B                      |
  54 | [LiteVideo](http://github.com/enjoy-digital/litevideo)       | [![](https://travis-ci.com/enjoy-digital/litevideo.svg?branch=master)](https://travis-ci.com/enjoy-digital/litevideo)    | VGA, DVI, HDMI                     |
  55 | [LiteScope](http://github.com/enjoy-digital/litescope)       | [![](https://travis-ci.com/enjoy-digital/litescope.svg?branch=master)](https://travis-ci.com/enjoy-digital/litescope)    | Logic analyzer  |
  56
  57 # Sub-packages
  58 **litex.gen**
  59 Provides specific or experimental modules to generate HDL that are not integrated in Migen.
  60
  61 **litex.build:**
  62 Provides tools to build FPGA bitstreams (interface to vendor toolchains) and to simulate HDL code or full SoCs.
  63
  64 **litex.soc:**
  65 Provides definitions/modules to build cores (bus, bank, flow), cores and tools to build a SoC from such cores.
  66
  67 **litex.boards:**
  68 Provides platforms and targets for the supported boards. All Migen's platforms can also be used in LiteX. The boards present in the LiteX repository are the official ones that are used for development/CI. More boards are available at: https://github.com/litex-hub/litex-boards
  69
  70 # Papers, Presentations, Tutorials, Links
  71 **FPGA lessons/tutorials:**
  72 - https://github.com/enjoy-digital/fpga_101
  73
  74 **OSDA paper/slides:**
  75 - https://osda.gitlab.io/19/1.1.pdf
  76 - https://osda.gitlab.io/19/1.1-slides.pdf
  77
  78 **Linux on LiteX-Vexriscv:**
  79 - https://github.com/litex-hub/linux-on-litex-vexriscv
  80
  81 **RISC-V Getting Started Guide:**
  82 - https://risc-v-getting-started-guide.readthedocs.io/en/latest/
  83
  84 **LiteX vs. Vivado First Impressions:**
  85 - https://www.bunniestudios.com/blog/?p=5018
  86
  87 **35C3 - Snakes and Rabbits - How CCC shaped an open hardware success:**
  88 - https://www.youtube.com/watch?v=AlmVxR0417c
  89
  90 **Tim has to many projects - LatchUp Edition:**
  91 https://www.youtube.com/watch?v=v7WrTmexod0
  92
  93 # Very Quick start guide (for newcomers)
  94 TimVideos.us has done an awesome job for setting up a LiteX environment easily in the litex-buildenv repo: https://github.com/timvideos/litex-buildenv
  95
  96 It's recommended for newcomers to go this way. Various FPGA boards are supported and multiple examples provided! You can even run Linux on your FPGA using LiteX very easily!
  97
  98 Migen documentation can be found here: https://m-labs.hk/migen/manual
  99
 100 # Quick start guide (for advanced users)
 101 0. Install Python 3.5+ and FPGA vendor's development tools.
 102 1. Install Migen/LiteX and the LiteX's cores:
 103 ```sh
 104 $ wget https://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py
 105 $ chmod +x litex_setup.py
 106 $ ./litex_setup.py init install --user (--user to install to user directory)
 107 ```
 108   Later, if you need to update all repositories:
 109 ```sh
 110 $ ./litex_setup.py update
 111 ```
 112 3. Install a RISC-V toolchain:
 113 ```sh
 114 $ wget https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14.tar.gz
 115 $ tar -xvf riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14.tar.gz
 116 $ export PATH=$PATH:$PWD/riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14/bin/
 117 ```
 118 4. Build the target of your board...:
 119   Go to litex-boards/litex_boards/xxyy/targets (xxyy being community/official/partner) and execute the target you want to build
 120
 121 5. ... and/or install Verilator and test LiteX on your computer:
 122   Download and install Verilator: http://www.veripool.org/
 123   On Fedora:
 124 ```sh
 125 $ sudo dnf install libevent-devel json-c-devel
 126 ```
 127   On Ubuntu:
 128 ```sh
 129 $ sudo apt install libevent-dev libjson-c-dev
 130 $ litex_sim
 131 ```
 132
 133 6. Run a terminal program on the board's serial port at 115200 8-N-1.
 134   You should get the BIOS prompt.
 135
 136 # Contact
 137 E-mail: florent@enjoy-digital.fr