README.md

   1 ![LiteX](https://raw.githubusercontent.com/enjoy-digital/litex/master/doc/litex.png)
   2 ```
   3               Copyright 2012-2020 / EnjoyDigital
   4 ```
   5 [![](https://travis-ci.com/enjoy-digital/litex.svg?branch=master)](https://travis-ci.com/enjoy-digital/litex)
   6 ![License](https://img.shields.io/badge/License-BSD%202--Clause-orange.svg)
   7 # Welcome to LiteX!
   8 LiteX is a FPGA design/SoC builder that can be used to build cores, create
   9 SoCs and full FPGA designs.
  10
  11 LiteX is based on Migen/MiSoC and provides specific building/debugging tools
  12 for a higher level of abstraction and compatibily with the LiteX core ecosystem.
  13
  14 Think of Migen as a toolbox to create FPGA designs in Python and LiteX as a
  15 SoC builder to create/develop/debug FPGA SoCs in Python.
  16
  17 # Typical LiteX design flow:
  18 ```
  19                         +---------------+
  20                         |FPGA toolchains|
  21                         +----^-----+----+
  22                              |     |
  23                           +--+-----v--+
  24          +-------+        |           |
  25          | Migen +-------->           |
  26          +-------+        |           |        Your design
  27                           |   LiteX   +---> ready to be used!
  28                           |           |
  29 +----------------------+  |           |
  30 |LiteX Cores Ecosystem +-->           |
  31 +----------------------+  +-^-------^-+
  32  (Eth, SATA, DRAM, USB,     |       |
  33   PCIe, Video, etc...)      +       +
  34                            board   target
  35                            file    file
  36 ```
  37 LiteX already supports various softcores CPUs: LM32, Mor1kx, PicoRV32, VexRiscv
  38 and is compatible with the LiteX's Cores Ecosystem:
  39
  40 | Name                                                         | Build Status                                                            | Description                   |
  41 | ------------------------------------------------------------ | ----------------------------------------------------------------------- | ----------------------------- |
  42 | [LiteDRAM](http://github.com/enjoy-digital/litedram)         | [![](https://travis-ci.org/enjoy-digital/litedram.svg?branch=master)](https://travis-ci.org/enjoy-digital/litedram)     | DRAM        |
  43 | [LiteEth](http://github.com/enjoy-digital/liteeth)           | [![](https://travis-ci.com/enjoy-digital/liteeth.svg?branch=master)](https://travis-ci.com/enjoy-digital/liteeth)       | Ethernet                      |
  44 | [LitePCIe](http://github.com/enjoy-digital/litepcie)         | [![](https://travis-ci.com/enjoy-digital/litepcie.svg?branch=master)](https://travis-ci.com/enjoy-digital/litepcie)     | PCIe                          |
  45 | [LiteSATA](http://github.com/enjoy-digital/litesata)         | [![](https://travis-ci.com/enjoy-digital/litesata.svg?branch=master)](https://travis-ci.com/enjoy-digital/litesata)     | SATA                          |
  46 | [LiteSDCard](http://github.com/enjoy-digital/litesdcard)     | [![](https://travis-ci.com/enjoy-digital/litesdcard.svg?branch=master)](https://travis-ci.com/enjoy-digital/litesdcard)   | SD card                       |
  47 | [LiteICLink](http://github.com/enjoy-digital/liteiclink)     | [![](https://travis-ci.com/enjoy-digital/liteiclink.svg?branch=master)](https://travis-ci.com/enjoy-digital/liteiclink)   | Inter-Chip communication      |
  48 | [LiteJESD204B](http://github.com/enjoy-digital/litejesd204b) | [![](https://travis-ci.com/enjoy-digital/litejesd204b.svg?branch=master)](https://travis-ci.com/enjoy-digital/litejesd204b) | JESD204B                      |
  49 | [LiteVideo](http://github.com/enjoy-digital/litevideo)       | [![](https://travis-ci.com/enjoy-digital/litevideo.svg?branch=master)](https://travis-ci.com/enjoy-digital/litevideo)    | VGA, DVI, HDMI                     |
  50 | [LiteScope](http://github.com/enjoy-digital/litescope)       | [![](https://travis-ci.com/enjoy-digital/litescope.svg?branch=master)](https://travis-ci.com/enjoy-digital/litescope)    | Logic analyzer  |
  51
  52 # Sub-packages
  53 **litex.gen**
  54 Provides specific or experimental modules to generate HDL that are not integrated in Migen.
  55
  56 **litex.build:**
  57 Provides tools to build FPGA bitstreams (interface to vendor toolchains) and to simulate HDL code or full SoCs.
  58
  59 **litex.soc:**
  60 Provides definitions/modules to build cores (bus, bank, flow), cores and tools to build a SoC from such cores.
  61
  62 **litex.boards:**
  63 Provides platforms and targets for the supported boards. All Migen's platforms can also be used in LiteX. The boards present in the LiteX repository are the official ones that are used for development/CI. More boards are available at: https://github.com/litex-hub/litex-boards
  64
  65 # Papers, Presentations, Tutorials, Links
  66 **FPGA lessons/tutorials:**
  67 - https://github.com/enjoy-digital/fpga_101
  68
  69 **OSDA paper/slides:**
  70 - https://osda.gitlab.io/19/1.1.pdf
  71 - https://osda.gitlab.io/19/1.1-slides.pdf
  72
  73 **Linux on LiteX-Vexriscv:**
  74 - https://github.com/litex-hub/linux-on-litex-vexriscv
  75
  76 **RISC-V Getting Started Guide:**
  77 - https://risc-v-getting-started-guide.readthedocs.io/en/latest/
  78
  79 **LiteX vs. Vivado First Impressions:**
  80 - https://www.bunniestudios.com/blog/?p=5018
  81
  82 **35C3 - Snakes and Rabbits - How CCC shaped an open hardware success:**
  83 - https://www.youtube.com/watch?v=AlmVxR0417c
  84
  85 **Tim has to many projects - LatchUp Edition:**
  86 https://www.youtube.com/watch?v=v7WrTmexod0
  87
  88 # Very Quick start guide (for newcomers)
  89 TimVideos.us has done an awesome job for setting up a LiteX environment easily in the litex-buildenv repo: https://github.com/timvideos/litex-buildenv
  90
  91 It's recommended for newcomers to go this way. Various FPGA boards are supported and multiple examples provided! You can even run Linux on your FPGA using LiteX very easily!
  92
  93 Migen documentation can be found here: https://m-labs.hk/migen/manual
  94
  95 # Quick start guide (for advanced users)
  96 0. Install Python 3.5+ and FPGA vendor's development tools.
  97 1. Install Migen/LiteX and the LiteX's cores:
  98 ```sh
  99 $ wget https://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py
 100 $ chmod +x litex_setup.py
 101 $ ./litex_setup.py init install --user (--user to install to user directory)
 102 ```
 103   Later, if you need to update all repositories:
 104 ```sh
 105 $ ./litex_setup.py update
 106 ```
 107 3. Install a RISC-V toolchain:
 108 ```sh
 109 $ wget https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14.tar.gz
 110 $ tar -xvf riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14.tar.gz
 111 $ export PATH=$PATH:$PWD/riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14/bin/
 112 ```
 113 4. Build the target of your board...:
 114   Go to litex-boards/litex_boards/xxyy/targets (xxyy being community/official/partner) and execute the target you want to build
 115
 116 5. ... and/or install Verilator and test LiteX on your computer:
 117   Download and install Verilator: http://www.veripool.org/
 118   On Fedora:
 119 ```sh
 120 $ sudo dnf install libevent-devel json-c-devel
 121 ```
 122   On Ubuntu:
 123 ```sh
 124 $ sudo apt install libevent-dev libjson-c-dev
 125 $ litex_sim
 126 ```
 127
 128 6. Run a terminal program on the board's serial port at 115200 8-N-1.
 129   You should get the BIOS prompt.
 130
 131 # Contact
 132 E-mail: florent@enjoy-digital.fr