README.md

   1 <p align="center"><img src="https://raw.githubusercontent.com/enjoy-digital/litex/master/doc/litex.png"></p>
   2
   3 ```
   4                           Copyright 2012-2020 / Enjoy-Digital
   5 ```
   6 [![](https://travis-ci.com/enjoy-digital/litex.svg?branch=master)](https://travis-ci.com/enjoy-digital/litex)
   7 ![License](https://img.shields.io/badge/License-BSD%202--Clause-orange.svg)
   8 # Welcome to LiteX!
   9
  10 LiteX is a Migen/MiSoC based Core/SoC builder that provides the infrastructure to easily create Cores/SoCs (with or without CPU).
  11 The common components of a SoC are provided directly: Buses and Streams (Wishbone, AXI, Avalon-ST), Interconnect, Common cores (RAM, ROM, Timer, UART, etc...), CPU wrappers/integration, etc... and SoC creation capabilities can be greatly extended with the ecosystem of LiteX cores (DRAM, PCIe, Ethernet, SATA, etc...) than can be integrated/simulated/build easily with LiteX. It also provides build backends for open-source and vendors toolchains.
  12
  13 Think of Migen as a toolbox to create FPGA designs in Python and LiteX as a
  14 SoC builder to create/develop/debug FPGA SoCs in Python.
  15
  16 **A question or want to get in touch? Our IRC channel is [#litex at freenode.net](https://webchat.freenode.net/?channels=litex)**
  17
  18 # Typical LiteX design flow:
  19 ```
  20                                       +---------------+
  21                                       |FPGA toolchains|
  22                                       +----^-----+----+
  23                                            |     |
  24                                         +--+-----v--+
  25                        +-------+        |           |
  26                        | Migen +-------->           |
  27                        +-------+        |           |        Your design
  28                                         |   LiteX   +---> ready to be used!
  29                                         |           |
  30               +----------------------+  |           |
  31               |LiteX Cores Ecosystem +-->           |
  32               +----------------------+  +-^-------^-+
  33                (Eth, SATA, DRAM, USB,     |       |
  34                 PCIe, Video, etc...)      +       +
  35                                          board   target
  36                                          file    file
  37 ```
  38 LiteX already supports various softcores CPUs: VexRiscv, Rocket, LM32, Mor1kx, PicoRV32 and is compatible with the LiteX's Cores Ecosystem:
  39
  40 | Name                                                         | Build Status                                                            | Description                   |
  41 | ------------------------------------------------------------ | ----------------------------------------------------------------------- | ----------------------------- |
  42 | [LiteDRAM](http://github.com/enjoy-digital/litedram)         | [![](https://travis-ci.org/enjoy-digital/litedram.svg?branch=master)](https://travis-ci.org/enjoy-digital/litedram)     | DRAM        |
  43 | [LiteEth](http://github.com/enjoy-digital/liteeth)           | [![](https://travis-ci.com/enjoy-digital/liteeth.svg?branch=master)](https://travis-ci.com/enjoy-digital/liteeth)       | Ethernet                      |
  44 | [LitePCIe](http://github.com/enjoy-digital/litepcie)         | [![](https://travis-ci.com/enjoy-digital/litepcie.svg?branch=master)](https://travis-ci.com/enjoy-digital/litepcie)     | PCIe                          |
  45 | [LiteSATA](http://github.com/enjoy-digital/litesata)         | [![](https://travis-ci.com/enjoy-digital/litesata.svg?branch=master)](https://travis-ci.com/enjoy-digital/litesata)     | SATA                          |
  46 | [LiteSDCard](http://github.com/enjoy-digital/litesdcard)     | [![](https://travis-ci.com/enjoy-digital/litesdcard.svg?branch=master)](https://travis-ci.com/enjoy-digital/litesdcard)   | SD card                       |
  47 | [LiteICLink](http://github.com/enjoy-digital/liteiclink)     | [![](https://travis-ci.com/enjoy-digital/liteiclink.svg?branch=master)](https://travis-ci.com/enjoy-digital/liteiclink)   | Inter-Chip communication      |
  48 | [LiteJESD204B](http://github.com/enjoy-digital/litejesd204b) | [![](https://travis-ci.com/enjoy-digital/litejesd204b.svg?branch=master)](https://travis-ci.com/enjoy-digital/litejesd204b) | JESD204B                      |
  49 | [LiteVideo](http://github.com/enjoy-digital/litevideo)       | [![](https://travis-ci.com/enjoy-digital/litevideo.svg?branch=master)](https://travis-ci.com/enjoy-digital/litevideo)    | VGA, DVI, HDMI                     |
  50 | [LiteScope](http://github.com/enjoy-digital/litescope)       | [![](https://travis-ci.com/enjoy-digital/litescope.svg?branch=master)](https://travis-ci.com/enjoy-digital/litescope)    | Logic analyzer  |
  51
  52 Combining LiteX with the ecosystem of cores allows the creation of complex SoCs such as the one below
  53 created for the NeTV2 board to do HDMI capture/playback over PCIe:
  54
  55 <p align="center"><img width="800" src="https://raw.githubusercontent.com/enjoy-digital/netv2/master/doc/architecture.png"></p>
  56
  57 # Papers, Presentations, Tutorials, Links
  58 **FPGA lessons/tutorials:**
  59 - https://github.com/enjoy-digital/fpga_101
  60
  61 **Migen tutorial:**
  62 - https://m-labs.hk/migen/manual
  63
  64 **OSDA 2019 paper/slides:**
  65 - https://osda.gitlab.io/19/1.1.pdf
  66 - https://osda.gitlab.io/19/1.1-slides.pdf
  67
  68 **Linux on LiteX-Vexriscv:**
  69 - https://github.com/litex-hub/linux-on-litex-vexriscv
  70
  71 **RISC-V Getting Started Guide:**
  72 - https://risc-v-getting-started-guide.readthedocs.io/en/latest/
  73
  74 **LiteX vs. Vivado First Impressions:**
  75 - https://www.bunniestudios.com/blog/?p=5018
  76
  77 **35C3 - Snakes and Rabbits - How CCC shaped an open hardware success:**
  78 - https://www.youtube.com/watch?v=AlmVxR0417c
  79
  80 **Tim has to many projects - LatchUp Edition:**
  81 https://www.youtube.com/watch?v=v7WrTmexod0
  82
  83
  84 # Sub-packages
  85 **litex.gen**
  86 Provides specific or experimental modules to generate HDL that are not integrated in Migen.
  87
  88 **litex.build:**
  89 Provides tools to build FPGA bitstreams (interface to vendor toolchains) and to simulate HDL code or full SoCs.
  90
  91 **litex.soc:**
  92 Provides definitions/modules to build cores (bus, bank, flow), cores and tools to build a SoC from such cores.
  93
  94 **litex.boards:**
  95 Provides platforms and targets for the supported boards. All Migen's platforms can also be used in LiteX. The boards present in the LiteX repository are the official ones that are used for development/CI. More boards are available at: https://github.com/litex-hub/litex-boards
  96
  97 # Quick start guide
  98 0. Install Python 3.5+ and FPGA vendor's development tools.
  99 1. Install Migen/LiteX and the LiteX's cores:
 100
 101 On MacOS, make sure you have [HomeBrew](https://brew.sh) installed. Then do, ``brew install wget``.
 102
 103 ```sh
 104 $ wget https://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py
 105 $ chmod +x litex_setup.py
 106 $ ./litex_setup.py init install --user (--user to install to user directory)
 107 ```
 108   Later, if you need to update all repositories:
 109 ```sh
 110 $ ./litex_setup.py update
 111 ```
 112 3. Install a RISC-V toolchain:
 113
 114 For Linux:
 115 ```sh
 116 $ wget https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14.tar.gz
 117 $ tar -xvf riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14.tar.gz
 118 $ export PATH=$PATH:$PWD/riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14/bin/
 119 ```
 120 MacOS:
 121 ```sh
 122 $ wget https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-8.3.0-2019.08.0-x86_64-apple-darwin.tar.gz
 123 $ tar -xvf riscv64-unknown-elf-gcc-8.3.0-2019.08.0-x86_64-apple-darwin.tar.gz
 124 $ export PATH=$PATH:$PWD/riscv64-unknown-elf-gcc-8.3.0-2019.08.0-x86_64-apple-darwin/bin/
 125 ```
 126 4. Build the target of your board...:
 127   Go to litex-boards/litex_boards/xxyy/targets (xxyy being community/official/partner) and execute the target you want to build
 128
 129 5. ... and/or install [Verilator](http://www.veripool.org/) and test LiteX on your computer
 130
 131 On Fedora:
 132 ```sh
 133 $ sudo dnf install libevent-devel json-c-devel
 134 ```
 135 On Ubuntu:
 136 ```sh
 137 $ sudo apt install libevent-dev libjson-c-dev verilator
 138 $ litex_sim
 139 ```
 140 On MacOS:
 141
 142
 143 ```sh
 144 $ brew install json-c verilator libevent
 145 $ brew cask install tuntap
 146 $ litex_sim
 147 ```
 148
 149 6. Run a terminal program on the board's serial port at 115200 8-N-1.
 150
 151   You should get the BIOS prompt like the one below.
 152
 153 <p align="center"><img src="https://raw.githubusercontent.com/enjoy-digital/litex/master/doc/bios_screenshot.png"></p>
 154
 155 # Community
 156
 157 <p align="center"><img src="https://raw.githubusercontent.com/enjoy-digital/litex/master/doc/litex-hub.png" width="400"></p>
 158
 159 LiteX has been initially developed by EnjoyDigital to create custom SoCs/Systems for our clients
 160 (and we are still using it for that purpose :)); but over the years a friendly community has grown
 161 around LiteX and the ecosystem of cores. Feedbacks and contributions have already greatly improved
 162 the project, EnjoyDigital still leads the development but it is now a community project and collaborative
 163 projects created around/with LiteX can be found at https://github.com/litex-hub.
 164
 165 # Contact
 166 E-mail: florent@enjoy-digital.fr