TLB/src/CamEntry.py

   1 from nmigen import Module, Signal
   2
   3 # Content Addressable Memory (CAM) Entry
   4 # The purpose of this module is to represent an entry within a CAM.
   5 # This module when given a read command will compare  the given key
   6 # and output whether a match was found or not. When given a write
   7 # command it will write the given key and data into internal registers.
   8 class CamEntry:
   9
  10     # Arguments:
  11     #  key_size: (bit count) The size of the key
  12     #  data_size: (bit count) The size of the data
  13     def __init__(self, key_size, data_size):
  14         # Internal
  15         self.key = Signal(key_size)
  16
  17         # Input
  18         self.command = Signal(2) # 00 => NA 01 => Read 10 => Write 11 => Reserve
  19         self.key_in = Signal(key_size) # Reference key for the CAM
  20         self.data_in = Signal(data_size) # Data input when writing
  21
  22         # Output
  23         self.match = Signal(1) # Result of the internal/input key comparison
  24         self.data = Signal(data_size)
  25
  26
  27     def get_fragment(self, platform=None):
  28         m = Module()
  29         with m.Switch(self.command):
  30             with m.Case("01"):
  31                 with m.If(self.key_in == self.key):
  32                     m.d.sync += self.match.eq(1)
  33                 with m.Else():
  34                     m.d.sync += self.match.eq(0)
  35             with m.Case("10"):
  36                 m.d.sync += [
  37                     self.key.eq(self.key_in),
  38                     self.data.eq(self.data_in),
  39                     self.match.eq(0)
  40                 ]
  41             with m.Case():
  42                 m.d.sync += self.match.eq(0)
  43
  44         return m