comments and whitespace cleanup
[soc.git] / TLB / src / CamEntry.py
1 from nmigen import Module, Signal
2
3 class CamEntry:
4 """ Content Addressable Memory (CAM) Entry
5
6 The purpose of this module is to represent an entry within a CAM.
7 This module when given a read command will compare the given key
8 and output whether a match was found or not. When given a write
9 command it will write the given key and data into internal registers.
10 """
11
12 def __init__(self, key_size, data_size):
13 """ Arguments:
14 * key_size: (bit count) The size of the key
15 * data_size: (bit count) The size of the data
16 """
17 # Internal
18 self.key = Signal(key_size)
19
20 # Input
21 self.command = Signal(2) # 00 => NA 01 => Read 10 => Write 11 => Reset
22 self.key_in = Signal(key_size) # Reference key for the CAM
23 self.data_in = Signal(data_size) # Data input when writing
24
25 # Output
26 self.match = Signal(1) # Result of the internal/input key comparison
27 self.data = Signal(data_size)
28
29 def elaborate(self, platform=None):
30 m = Module()
31 with m.Switch(self.command):
32 with m.Case("00"):
33 m.d.sync += self.match.eq(0)
34 with m.Case("01"):
35 with m.If(self.key_in == self.key):
36 m.d.sync += self.match.eq(1)
37 with m.Else():
38 m.d.sync += self.match.eq(0)
39 with m.Case("10"):
40 m.d.sync += [
41 self.key.eq(self.key_in),
42 self.data.eq(self.data_in),
43 self.match.eq(0)
44 ]
45 with m.Case():
46 m.d.sync += [
47 self.match.eq(0),
48 self.data.eq(0),
49 self.key.eq(0)
50 ]
51
52 return m