TLB/src/VectorAssembler.py

   1 from nmigen import Array, Module, Signal
   2 from nmigen.cli import main
   3
   4 class VectorAssembler():
   5     """ Vector Assembler
   6
   7         The purpose of this module is to take a generic number of inputs
   8         and cleanly combine them into one vector. While this is very much
   9         possible through raw code it may result in a very unfortunate sight
  10         in a yosys graph. Thus this class was born! No more will ugly loops
  11         exist in my graphs! Get outta here ya goddam Lochness Monster.
  12     """
  13     def __init__(self, width):
  14         """ Arguments:
  15             * width: (bit count) The desiered size of the output vector
  16
  17         """
  18         # Internal
  19         self.width = width
  20
  21         # Input
  22         self.input = Array(Signal(1) for index in range(width))
  23
  24         # Output
  25         self.o = Signal(width)
  26
  27     def elaborate(self, platform=None):
  28         m = Module()
  29         for index in range(self.width):
  30             m.d.comb += self.o[index].eq(self.input[index])
  31
  32         return m