TLB/test/test_cam.py

   1 import sys
   2 sys.path.append("../src")
   3 sys.path.append("../../TestUtil")
   4
   5 from nmigen.compat.sim import run_simulation
   6
   7 from Cam import Cam
   8
   9 from test_helper import assert_eq, assert_ne
  10
  11 def set_cam(dut, e, we, a, d):
  12     yield dut.enable.eq(e)
  13     yield dut.write_enable.eq(we)
  14     yield dut.address_in.eq(a)
  15     yield dut.data_in.eq(d)
  16     yield
  17
  18 def check_multiple_match(dut, mm, op):
  19     out_mm = yield dut.multiple_match
  20     if op == 0:
  21         assert_eq("Multiple Match", out_mm, mm)
  22     else:
  23         assert_ne("Multiple Match", out_mm, mm)
  24
  25 def check_single_match(dut, sm, op):
  26     out_sm = yield dut.single_match
  27     if op == 0:
  28         assert_eq("Single Match", out_sm, sm)
  29     else:
  30         assert_ne("Single Match", out_sm, sm)
  31
  32 def check_match_address(dut, ma, op):
  33     out_ma = yield dut.match_address
  34     if op == 0:
  35         assert_eq("Match Address", out_ma, ma)
  36     else:
  37         assert_ne("Match Address", out_ma, ma)
  38
  39 def check_all(dut, multiple_match, single_match, match_address, mm_op, sm_op, ma_op):
  40     yield from check_multiple_match(dut, multiple_match, mm_op)
  41     yield from check_single_match(dut, single_match, sm_op)
  42     yield from check_match_address(dut, match_address, ma_op)
  43
  44
  45
  46 def testbench(dut):
  47     # NA
  48     enable = 0
  49     write_enable = 0
  50     address = 0
  51     data = 0
  52     single_match = 0
  53     yield from set_cam(dut, enable, write_enable, address, data)
  54     yield
  55     yield from check_single_match(dut, single_match, 0)
  56
  57     # Read Miss Multiple
  58     # Note that the default starting entry data bits are all 0
  59     enable = 1
  60     write_enable = 0
  61     address = 0
  62     data = 0
  63     multiple_match = 1
  64     single_match = 0
  65     yield from set_cam(dut, enable, write_enable, address, data)
  66     yield
  67     yield from check_multiple_match(dut, multiple_match, 0)
  68
  69     # Read Miss
  70     # Note that the default starting entry data bits are all 0
  71     enable = 1
  72     write_enable = 0
  73     address = 0
  74     data = 1
  75     multiple_match = 0
  76     single_match = 0
  77     yield from set_cam(dut, enable, write_enable, address, data)
  78     yield
  79     yield from check_single_match(dut, single_match, 0)
  80
  81     # Write Entry 0
  82     enable = 1
  83     write_enable = 1
  84     address = 0
  85     data = 4
  86     multiple_match = 0
  87     single_match = 0
  88     yield from set_cam(dut, enable, write_enable, address, data)
  89     yield
  90     yield from check_single_match(dut, single_match, 0)
  91
  92     # Read Hit Entry 0
  93     enable = 1
  94     write_enable = 0
  95     address = 0
  96     data = 4
  97     multiple_match = 0
  98     single_match = 1
  99     yield from set_cam(dut, enable, write_enable, address, data)
 100     yield
 101     yield from check_all(dut, multiple_match, single_match, address, 0, 0, 0)
 102
 103     # Search Hit
 104     enable = 1
 105     write_enable = 0
 106     address = 0
 107     data = 4
 108     multiple_match = 0
 109     single_match = 1
 110     yield from set_cam(dut, enable, write_enable, address, data)
 111     yield
 112     yield from check_all(dut, multiple_match, single_match, address, 0, 0, 0)
 113
 114     # Search Miss
 115     enable = 1
 116     write_enable = 0
 117     address = 0
 118     data = 5
 119     single_match = 0
 120     yield from set_cam(dut, enable, write_enable, address, data)
 121     yield
 122     yield from check_single_match(dut, single_match, 0)
 123
 124     yield
 125
 126
 127 if __name__ == "__main__":
 128     dut = Cam(4, 4)
 129     run_simulation(dut, testbench(dut), vcd_name="Waveforms/cam_test.vcd")
 130     print("Cam Unit Test Success")