Adding more logic to test
[soc.git] / TLB / test / test_cam.py
1 import sys
2 sys.path.append("../src")
3 sys.path.append("../../TestUtil")
4
5 from nmigen.compat.sim import run_simulation
6
7 from Cam import Cam
8
9 from test_helper import assert_eq, assert_ne
10
11 def set_cam(dut, c, a, k, d):
12 print("asdf")
13 yield dut.command.eq(c)
14 yield dut.address.eq(a)
15 yield dut.key_in.eq(k)
16 yield dut.data_in.eq(d)
17 yield
18 yield dut.command.eq(0)
19 yield dut.address.eq(0)
20 yield dut.key_in.eq(0)
21 yield dut.data_in.eq(0)
22 yield
23
24 def check_data_hit(dut, dh, op):
25 out_dh = yield dut.data_hit
26 if op == 0:
27 assert_eq("Data Hit", out_dh, dh)
28 else:
29 assert_ne("Data Hit", out_dh, dh)
30
31 def check_data(dut, d, op):
32 out_d = yield dut.data_out
33 if op == 0:
34 assert_eq("Data", out_d, d)
35 else:
36 assert_ne("Data", out_d, d)
37
38 def check_all(dut, data_hit, data, dh_op, d_op):
39 yield from check_data_hit(dut, data_hit, dh_op)
40 yield from check_data(dut, data, d_op)
41
42
43 def testbench(dut):
44 # NA
45 command = 0
46 address = 0
47 key = 0
48 data = 0
49 data_hit = 0
50 yield from set_cam(dut, command, address, key, data)
51 #yield from check_data_hit(dut, data_hit, 0)
52
53 # Search
54 command = 3
55 address = 0
56 key = 0
57 data = 0
58 data_hit = 0
59 yield from set_cam(dut, command, address, key, data)
60 #yield from check_data_hit(dut, data_hit, 0)
61
62 # Write Entry 0
63 command = 2
64 address = 0
65 key = 5
66 data = 4
67 data_hit = 0
68 yield from set_cam(dut, command, address, key, data)
69 #yield from check_data_hit(dut, data_hit, 0)
70
71 # Read Entry 0
72 command = 1
73 address = 0
74 key = 0
75 data = 4
76 data_hit = 0
77 yield from set_cam(dut, command, address, key, data)
78 #yield from check_all(dut, data_hit, data, 0, 0)
79
80 # Search
81 command = 3
82 address = 0
83 key = 5
84 data = 4
85 data_hit = 1
86 yield from set_cam(dut, command, address, key, data)
87 #yield from check_all(dut, data_hit, data, 0, 0)
88
89 yield
90
91
92 if __name__ == "__main__":
93 dut = Cam(4, 4, 4)
94 run_simulation(dut, testbench(dut), vcd_name="Waveforms/cam_test.vcd")
95 print("Cam Unit Test Success")