TLB/test/test_cam.py

   1 import sys
   2 sys.path.append("../src")
   3 sys.path.append("../../TestUtil")
   4
   5 from nmigen.compat.sim import run_simulation
   6
   7 from Cam import Cam
   8
   9 from test_helper import assert_eq, assert_ne, assert_op
  10
  11 # This function allows for the easy setting of values to the Cam
  12 # Arguments:
  13 #   dut: The Cam being tested
  14 #   e (Enable): Whether the block is going to be enabled
  15 #   we (Write Enable): Whether the Cam will write on the next cycle
  16 #   a (Address): Where the data will be written if write enable is high
  17 #   d (Data): Either what we are looking for or will write to the address
  18 def set_cam(dut, e, we, a, d):
  19     yield dut.enable.eq(e)
  20     yield dut.write_enable.eq(we)
  21     yield dut.address_in.eq(a)
  22     yield dut.data_in.eq(d)
  23     yield
  24
  25 # Checks the multiple match of the Cam
  26 # Arguments:
  27 #   dut: The Cam being tested
  28 #   mm (Multiple Match): The expected match result
  29 #   op (Operation): (0 => ==), (1 => !=)
  30 def check_multiple_match(dut, mm, op):
  31     out_mm = yield dut.multiple_match
  32     assert_op("Multiple Match", out_mm, mm, op)
  33
  34 # Checks the single match of the Cam
  35 # Arguments:
  36 #   dut: The Cam being tested
  37 #   sm (Single Match): The expected match result
  38 #   op (Operation): (0 => ==), (1 => !=)
  39 def check_single_match(dut, sm, op):
  40     out_sm = yield dut.single_match
  41     assert_op("Single Match", out_sm, sm, op)
  42
  43 # Checks the address output of the Cam
  44 # Arguments:
  45 #   dut: The Cam being tested
  46 #   ma (Match Address): The expected match result
  47 #   op (Operation): (0 => ==), (1 => !=)
  48 def check_match_address(dut, ma, op):
  49     out_ma = yield dut.match_address
  50     assert_op("Match Address", out_ma, ma, op)
  51
  52 # Checks the state of the Cam
  53 # Arguments:
  54 #   dut: The Cam being tested
  55 #   sm (Single Match): The expected match result
  56 #   mm (Multiple Match): The expected match result
  57 #   ma: (Match Address): The expected address output
  58 #   ss_op (Operation): Operation for the match assertion (0 => ==), (1 => !=)
  59 #   mm_op (Operation): Operation for the match assertion (0 => ==), (1 => !=)
  60 #   ma_op (Operation): Operation for the address assertion (0 => ==), (1 => !=)
  61 def check_all(dut, mm, sm, ma, mm_op, sm_op, ma_op):
  62     yield from check_multiple_match(dut, mm, mm_op)
  63     yield from check_single_match(dut, sm, sm_op)
  64     yield from check_match_address(dut, ma, ma_op)
  65
  66 def testbench(dut):
  67     # NA
  68     enable = 0
  69     write_enable = 0
  70     address = 0
  71     data = 0
  72     single_match = 0
  73     yield from set_cam(dut, enable, write_enable, address, data)
  74     yield
  75     yield from check_single_match(dut, single_match, 0)
  76
  77     # Read Miss Multiple
  78     # Note that the default starting entry data bits are all 0
  79     enable = 1
  80     write_enable = 0
  81     address = 0
  82     data = 0
  83     multiple_match = 1
  84     single_match = 0
  85     yield from set_cam(dut, enable, write_enable, address, data)
  86     yield
  87     yield from check_multiple_match(dut, multiple_match, 0)
  88
  89     # Read Miss
  90     # Note that the default starting entry data bits are all 0
  91     enable = 1
  92     write_enable = 0
  93     address = 0
  94     data = 1
  95     multiple_match = 0
  96     single_match = 0
  97     yield from set_cam(dut, enable, write_enable, address, data)
  98     yield
  99     yield from check_single_match(dut, single_match, 0)
 100
 101     # Write Entry 0
 102     enable = 1
 103     write_enable = 1
 104     address = 0
 105     data = 4
 106     multiple_match = 0
 107     single_match = 0
 108     yield from set_cam(dut, enable, write_enable, address, data)
 109     yield
 110     yield from check_single_match(dut, single_match, 0)
 111
 112     # Read Hit Entry 0
 113     enable = 1
 114     write_enable = 0
 115     address = 0
 116     data = 4
 117     multiple_match = 0
 118     single_match = 1
 119     yield from set_cam(dut, enable, write_enable, address, data)
 120     yield
 121     yield from check_all(dut, multiple_match, single_match, address, 0, 0, 0)
 122
 123     # Search Hit
 124     enable = 1
 125     write_enable = 0
 126     address = 0
 127     data = 4
 128     multiple_match = 0
 129     single_match = 1
 130     yield from set_cam(dut, enable, write_enable, address, data)
 131     yield
 132     yield from check_all(dut, multiple_match, single_match, address, 0, 0, 0)
 133
 134     # Search Miss
 135     enable = 1
 136     write_enable = 0
 137     address = 0
 138     data = 5
 139     single_match = 0
 140     yield from set_cam(dut, enable, write_enable, address, data)
 141     yield
 142     yield from check_single_match(dut, single_match, 0)
 143
 144     # Multiple Match test
 145     # Write Entry 1
 146     enable = 1
 147     write_enable = 1
 148     address = 1
 149     data = 5
 150     multiple_match = 0
 151     single_match = 0
 152     yield from set_cam(dut, enable, write_enable, address, data)
 153     yield
 154     yield from check_single_match(dut, single_match, 0)
 155
 156     # Write Entry 2
 157     # Same data as Entry 1
 158     enable = 1
 159     write_enable = 1
 160     address = 2
 161     data = 5
 162     multiple_match = 0
 163     single_match = 0
 164     yield from set_cam(dut, enable, write_enable, address, data)
 165     yield
 166     yield from check_single_match(dut, single_match, 0)
 167
 168     # Read Data 5
 169     enable = 1
 170     write_enable = 0
 171     address = 1
 172     data = 5
 173     multiple_match = 1
 174     single_match = 0
 175     yield from set_cam(dut, enable, write_enable, address, data)
 176     yield
 177     yield from check_all(dut, multiple_match, single_match, address,0,0,0)
 178
 179     yield
 180
 181
 182 if __name__ == "__main__":
 183     dut = Cam(4, 4)
 184     run_simulation(dut, testbench(dut), vcd_name="Waveforms/test_cam.vcd")
 185     print("Cam Unit Test Success")