TLB/test/test_cam.py

   1 from nmigen.compat.sim import run_simulation
   2
   3 from test_helper import check
   4 from Cam import Cam
   5
   6 def set_cam(dut, c, a, k, d):
   7     yield dut.command.eq(c)
   8     yield dut.address.eq(a)
   9     yield dut.key_in.eq(k)
  10     yield dut.data_in.eq(d)
  11     yield
  12
  13 def check_data_hit(dut, data_hit, op):
  14     out_dh = yield dut.data_hit
  15     yield from check("Data Hit", out_dh, data_hit, op)
  16
  17 def check_data(dut, data, op):
  18     out_d = yield dut.data
  19     yield from check("Data", out_d, data, op)
  20
  21 def check_all(dut, data_hit, data, dh_op, d_op):
  22     yield from check_data_hit(dut, data_hit, dh_op)
  23     yield from check_data(dut, data, d_op)
  24
  25
  26 def testbench(dut):
  27     # NA
  28     command = 0
  29     address = 0
  30     key = 0
  31     data = 0
  32     data_hit = 0
  33     yield from set_cam(dut, command, address, key, data)
  34     yield from check_data_hit(dut, data_hit, 0)
  35
  36     # Search
  37     command = 3
  38     address = 0
  39     key = 0
  40     data = 0
  41     data_hit = 0
  42     yield from set_cam(dut, command, address, key, data)
  43     yield from check_data_hit(dut, data_hit, 0)
  44
  45     # Write Entry 0
  46     command = 1
  47     address = 0
  48     key = 5
  49     data = 4
  50     data_hit = 1
  51     yield from set_cam(dut, command, address, key, data)
  52     yield from check_data_hit(dut, data_hit, 0)
  53
  54 if __name__ == "__main__":
  55     dut = Cam(4, 4, 4)
  56     run_simulation(dut, testbench(dut), vcd_name="Waveforms/cam_test.vcd")
  57     print("Cam Unit Test Success")