TLB/test/test_cam_entry.py

   1 import sys
   2 sys.path.append("../src")
   3 sys.path.append("../../TestUtil")
   4
   5 from nmigen.compat.sim import run_simulation
   6
   7 from test_helper import check
   8 from CamEntry import CamEntry
   9
  10 # This function allows for the easy setting of values to the Cam Entry
  11 # unless the key is incorrect
  12 # Arguments:
  13 #   dut: The CamEntry being tested
  14 #   c (command): NA (0), Read (1), Write (2), Reserve (3)
  15 #   k (key): The key to be set
  16 #   d (data): The data to be set
  17 def set_cam_entry(dut, c, k, d):
  18     # Write desired values
  19     yield dut.command.eq(c)
  20     yield dut.key_in.eq(k)
  21     yield dut.data_in.eq(d)
  22     yield
  23     # Reset all lines
  24     yield dut.command.eq(0)
  25     yield dut.key_in.eq(0)
  26     yield dut.data_in.eq(0)
  27     yield
  28
  29 # Checks the key state of the CAM entry
  30 # Arguments:
  31 #   dut: The CamEntry being tested
  32 #   k (Key): The expected key
  33 #   op (Operation): (0 => ==), (1 => !=)
  34 def check_key(dut, k, op):
  35     out_k = yield dut.key
  36     check("Key", out_k, k, op)
  37
  38 # Checks the data state of the CAM entry
  39 # Arguments:
  40 #   dut: The CamEntry being tested
  41 #   d (Data): The expected data
  42 #   op (Operation): (0 => ==), (1 => !=)
  43 def check_data(dut, d, op):
  44     out_d = yield dut.data
  45     check("Data", out_d, d, op)
  46
  47 # Checks the match state of the CAM entry
  48 # Arguments:
  49 #   dut: The CamEntry being tested
  50 #   m (Match): The expected match
  51 #   op (Operation): (0 => ==), (1 => !=)
  52 def check_match(dut, m, op):
  53     out_m = yield dut.match
  54     check("Match", out_m, m, op)
  55
  56 # Checks the state of the CAM entry
  57 # Arguments:
  58 #   dut: The CamEntry being tested
  59 #   k (key): The expected key
  60 #   d (data): The expected data
  61 #   m (match): The expected match
  62 #   k_op (Operation): The operation for the key assertion (0 => ==), (1 => !=)
  63 #   d_op (Operation): The operation for the data assertion (0 => ==), (1 => !=)
  64 #   m_op (Operation): The operation for the match assertion (0 => ==), (1 => !=)
  65 def check_all(dut, k, d, m, k_op, d_op, m_op):
  66     yield from check_key(dut, k, k_op)
  67     yield from check_data(dut, d, d_op)
  68     yield from check_match(dut, m, m_op)
  69
  70 # This testbench goes through the paces of testing the CamEntry module
  71 # It is done by writing and then reading various combinations of key/data pairs
  72 # and reading the results with varying keys to verify the resulting stored
  73 # data is correct.
  74 def testbench(dut):
  75     # Check write
  76     command = 2
  77     key = 1
  78     data = 1
  79     match = 0
  80     yield from set_cam_entry(dut, command, key, data)
  81     yield from check_all(dut, key, data, match, 0, 0, 0)
  82
  83     # Check read miss
  84     command = 1
  85     key = 2
  86     data = 1
  87     match = 0
  88     yield from set_cam_entry(dut, command, key, data)
  89     yield from check_all(dut, key, data, match, 1, 0, 0)
  90
  91     # Check read hit
  92     command = 1
  93     key = 1
  94     data = 1
  95     match = 1
  96     yield from set_cam_entry(dut, command, key, data)
  97     yield from check_all(dut, key, data, match, 0, 0, 0)
  98
  99     # Check overwrite
 100     command = 2
 101     key = 2
 102     data = 5
 103     match = 0
 104     yield from set_cam_entry(dut, command, key, data)
 105     yield
 106     yield from check_all(dut, key, data, match, 0, 0, 0)
 107
 108     # Check read hit
 109     command = 1
 110     key = 2
 111     data = 5
 112     match = 1
 113     yield from set_cam_entry(dut, command, key, data)
 114     yield from check_all(dut, key, data, match, 0, 0, 0)
 115
 116     # Extra clock cycle for waveform
 117     yield
 118
 119 if __name__ == "__main__":
 120     dut = CamEntry(4, 4)
 121     run_simulation(dut, testbench(dut), vcd_name="Waveforms/cam_entry_test.vcd")
 122     print("CamEntry Unit Test Success")