TLB/test/test_pte_entry.py

   1 import sys
   2 sys.path.append("../src")
   3 sys.path.append("../../TestUtil")
   4
   5 from nmigen.compat.sim import run_simulation
   6
   7 from PteEntry import PteEntry
   8
   9 from test_helper import assert_op
  10
  11 def set_entry(dut, i):
  12     yield dut.i.eq(i)
  13     yield
  14
  15 def check_dirty(dut, d, op):
  16     out_d = yield dut.d
  17     assert_op("Dirty", out_d, d, op)
  18
  19 def check_accessed(dut, a, op):
  20     out_a = yield dut.a
  21     assert_op("Accessed", out_a, a, op)
  22
  23 def check_global(dut, o, op):
  24     out = yield dut.g
  25     assert_op("Global", out, o, op)
  26
  27 def check_user(dut, o, op):
  28     out = yield dut.u
  29     assert_op("User Mode", out, o, op)
  30
  31 def check_xwr(dut, o, op):
  32     out = yield dut.xwr
  33     assert_op("XWR", out, o, op)
  34
  35 def check_asid(dut, o, op):
  36     out = yield dut.asid
  37     assert_op("ASID", out, o, op)
  38
  39 def check_pte(dut, o, op):
  40     out = yield dut.pte
  41     assert_op("ASID", out, o, op)
  42
  43 def check_valid(dut, v, op):
  44     out_v = yield dut.v
  45     assert_op("Valid", out_v, v, op)
  46
  47 def check_all(dut, d, a, g, u, xwr, v, asid, pte):
  48     yield from check_dirty(dut, d, 0)
  49     yield from check_accessed(dut, a, 0)
  50     yield from check_global(dut, g, 0)
  51     yield from check_user(dut, u, 0)
  52     yield from check_xwr(dut, xwr, 0)
  53     yield from check_asid(dut, asid, 0)
  54     yield from check_pte(dut, pte, 0)
  55     yield from check_valid(dut, v, 0)
  56
  57 def testbench(dut):
  58     # 80 bits represented. Ignore the MSB as it will be truncated
  59     # ASID is bits first 4 hex values (bits 64 - 78)
  60
  61     i = 0x7FFF0000000000000031
  62     dirty = 0
  63     access = 0
  64     glob = 1
  65     user = 1
  66     xwr = 0
  67     valid = 1
  68     asid = 0x7FFF
  69     pte = 0x0000000000000031
  70     yield from set_entry(dut, i)
  71     yield from check_all(dut, dirty, access, glob, user, xwr, valid, asid, pte)
  72
  73     i = 0x0FFF00000000000000FF
  74     dirty = 1
  75     access = 1
  76     glob = 1
  77     user = 1
  78     xwr = 7
  79     valid = 1
  80     asid = 0x0FFF
  81     pte = 0x00000000000000FF
  82     yield from set_entry(dut, i)
  83     yield from check_all(dut, dirty, access, glob, user, xwr, valid, asid, pte)
  84
  85     i = 0x0721000000001100001F
  86     dirty = 0
  87     access = 0
  88     glob = 0
  89     user = 1
  90     xwr = 7
  91     valid = 1
  92     asid = 0x0721
  93     pte = 0x000000001100001F
  94     yield from set_entry(dut, i)
  95     yield from check_all(dut, dirty, access, glob, user, xwr, valid, asid, pte)
  96
  97     yield
  98
  99
 100 if __name__ == "__main__":
 101     dut = PteEntry(15, 64);
 102     run_simulation(dut, testbench(dut), vcd_name="Waveforms/test_pte_entry.vcd")
 103     print("PteEntry Unit Test Success")