TLB/test/test_vector_assembler.py

   1 import sys
   2 sys.path.append("../src")
   3 sys.path.append("../../TestUtil")
   4
   5 from nmigen.compat.sim import run_simulation
   6
   7 from test_helper import assert_eq, assert_ne, assert_op
   8 from VectorAssembler import VectorAssembler
   9
  10 assembler_size = 4
  11
  12 def set_assembler(dut, input):
  13     assert len(input) == assembler_size
  14     for index in range(assembler_size):
  15         input_index = assembler_size - index - 1
  16         yield dut.input[index].eq(input[input_index])
  17     yield
  18
  19 def check_output(dut, o, op):
  20     out_o = yield dut.o
  21     assert_op("Output", out_o, o, op)
  22
  23
  24 def testbench(dut):
  25     input = [1, 1, 0, 0]
  26     output = 12
  27     yield from set_assembler(dut, input)
  28     yield from check_output(dut, output, 0)
  29
  30     input = [1, 1, 0, 1]
  31     output = 13
  32     yield from set_assembler(dut, input)
  33     yield from check_output(dut, output, 0)
  34
  35 if __name__ == "__main__":
  36     dut = VectorAssembler(assembler_size)
  37     run_simulation(dut, testbench(dut), vcd_name="Waveforms/test_vector_assembler.vcd")
  38     print("VectorAssembler Unit Test Success")