Adding test utility class to help with assertions and common testing functions
[soc.git] / TLB / test_cam_entry.py
1 from nmigen.compat.sim import run_simulation
2
3 from test_helper import check
4 from CamEntry import CamEntry
5
6 # This function allows for the easy setting of values to the Cam Entry
7 # unless the key is incorrect
8 # Arguments:
9 # dut: The CamEntry being tested
10 # c (command): NA (0), Read (1), Write (2), Reserve (3)
11 # k (key): The key to be set
12 # d (data): The data to be set
13 def set_cam_entry(dut, c, k, d):
14 # Write desired values
15 yield dut.command.eq(c)
16 yield dut.key_in.eq(k)
17 yield dut.data_in.eq(d)
18 yield
19 # Reset all lines
20 yield dut.command.eq(0)
21 yield dut.key_in.eq(0)
22 yield dut.data_in.eq(0)
23 yield
24
25 # Checks the key state of the CAM entry
26 # Arguments:
27 # dut: The CamEntry being tested
28 # k (Key): The expected key
29 # op (Operation): (0 => ==), (1 => !=)
30 def check_key(dut, k, op):
31 out_k = yield dut.key
32 check("Key", out_k, k, op)
33
34 # Checks the data state of the CAM entry
35 # Arguments:
36 # dut: The CamEntry being tested
37 # d (Data): The expected data
38 # op (Operation): (0 => ==), (1 => !=)
39 def check_data(dut, d, op):
40 out_d = yield dut.data
41 check("Data", out_d, d, op)
42
43 # Checks the match state of the CAM entry
44 # Arguments:
45 # dut: The CamEntry being tested
46 # m (Match): The expected match
47 # op (Operation): (0 => ==), (1 => !=)
48 def check_match(dut, m, op):
49 out_m = yield dut.match
50 check("Match", out_m, m, op)
51
52 # Checks the state of the CAM entry
53 # Arguments:
54 # dut: The CamEntry being tested
55 # k (key): The expected key
56 # d (data): The expected data
57 # m (match): The expected match
58 # k_op (Operation): The operation for the key assertion (0 => ==), (1 => !=)
59 # d_op (Operation): The operation for the data assertion (0 => ==), (1 => !=)
60 # m_op (Operation): The operation for the match assertion (0 => ==), (1 => !=)
61 def check_all(dut, k, d, m, k_op, d_op, m_op):
62 yield from check_key(dut, k, k_op)
63 yield from check_data(dut, d, d_op)
64 yield from check_match(dut, m, m_op)
65
66 # This testbench goes through the paces of testing the CamEntry module
67 # It is done by writing and then reading various combinations of key/data pairs
68 # and reading the results with varying keys to verify the resulting stored
69 # data is correct.
70 def testbench(dut):
71 # Check write
72 command = 2
73 key = 1
74 data = 1
75 match = 0
76 yield from set_cam_entry(dut, command, key, data)
77 yield from check_all(dut, key, data, match, 0, 0, 0)
78
79 # Check read miss
80 command = 1
81 key = 2
82 data = 1
83 match = 0
84 yield from set_cam_entry(dut, command, key, data)
85 yield from check_all(dut, key, data, match, 1, 0, 0)
86
87 # Check read hit
88 command = 1
89 key = 1
90 data = 1
91 match = 1
92 yield from set_cam_entry(dut, command, key, data)
93 yield from check_all(dut, key, data, match, 0, 0, 0)
94
95 # Check overwrite
96 command = 2
97 key = 2
98 data = 5
99 match = 0
100 yield from set_cam_entry(dut, command, key, data)
101 yield
102 yield from check_all(dut, key, data, match, 0, 0, 0)
103
104 # Check read hit
105 command = 1
106 key = 2
107 data = 5
108 match = 1
109 yield from set_cam_entry(dut, command, key, data)
110 yield from check_all(dut, key, data, match, 0, 0, 0)
111
112 # Extra clock cycle for waveform
113 yield
114
115 if __name__ == "__main__":
116 dut = CamEntry(4, 4)
117 run_simulation(dut, testbench(dut), vcd_name="Waveforms/cam_entry_test.vcd")
118 print("CamEntry Unit Test Success")