TLB/test_cam_entry.py

   1 from nmigen.compat.sim import run_simulation
   2
   3 from CamEntry import CamEntry
   4
   5 # This function allows for the easy setting of values to the Cam Entry
   6 # unless the key is incorrect
   7 # Arguments:
   8 #   dut: The CamEntry being tested
   9 #   c (command): NA (0), Read (1), Write (2), Reserve (3)
  10 #   k (key): The key to be set
  11 #   d (data): The data to be set
  12 def set_cam_entry(dut, c, k, d):
  13     # Write desired values
  14     yield dut.command.eq(c)
  15     yield dut.key_in.eq(k)
  16     yield dut.data_in.eq(d)
  17     yield
  18     # Reset all lines
  19     yield dut.command.eq(0)
  20     yield dut.key_in.eq(0)
  21     yield dut.data_in.eq(0)
  22     yield
  23
  24 # Verifies the given values via the requested operation
  25 # Arguments:
  26 #   p (Prefix): Appended to the front of the assert statement
  27 #   e (Expected): The expected value
  28 #   o (Output): The output result
  29 #   op (Operation): (0 => ==), (1 => !=)
  30 def check(p, o, e, op):
  31     if(op == 0):
  32         assert o == e, p + " Output " + str(o) + " Expected " + str(e)
  33     else:
  34         assert o != e, p + " Output " + str(o) + " Not Expecting " + str(e)
  35
  36 # Checks the key state of the CAM entry
  37 # Arguments:
  38 #   dut: The CamEntry being tested
  39 #   k (Key): The expected key
  40 #   op (Operation): (0 => ==), (1 => !=)
  41 def check_key(dut, k, op):
  42     out_k = yield dut.key
  43     check("Key", out_k, k, op)
  44
  45 # Checks the data state of the CAM entry
  46 # Arguments:
  47 #   dut: The CamEntry being tested
  48 #   d (Data): The expected data
  49 #   op (Operation): (0 => ==), (1 => !=)
  50 def check_data(dut, d, op):
  51     out_d = yield dut.data
  52     check("Data", out_d, d, op)
  53
  54 # Checks the match state of the CAM entry
  55 # Arguments:
  56 #   dut: The CamEntry being tested
  57 #   m (Match): The expected match
  58 #   op (Operation): (0 => ==), (1 => !=)
  59 def check_match(dut, m, op):
  60     out_m = yield dut.match
  61     check("Match", out_m, m, op)
  62
  63 # Checks the state of the CAM entry
  64 # Arguments:
  65 #   dut: The CamEntry being tested
  66 #   k (key): The expected key
  67 #   d (data): The expected data
  68 #   m (match): The expected match
  69 #   k_op (Operation): The operation for the key assertion (0 => ==), (1 => !=)
  70 #   d_op (Operation): The operation for the data assertion (0 => ==), (1 => !=)
  71 #   m_op (Operation): The operation for the match assertion (0 => ==), (1 => !=)
  72 def check_all(dut, k, d, m, k_op, d_op, m_op):
  73     yield from check_key(dut, k, k_op)
  74     yield from check_data(dut, d, d_op)
  75     yield from check_match(dut, m, m_op)
  76
  77 # This testbench goes through the paces of testing the CamEntry module
  78 # It is done by writing and then reading various combinations of key/data pairs
  79 # and reading the results with varying keys to verify the resulting stored
  80 # data is correct.
  81 def testbench(dut):
  82     # Check write
  83     command = 2
  84     key = 1
  85     data = 1
  86     match = 0
  87     yield from set_cam_entry(dut, command, key, data)
  88     yield from check_all(dut, key, data, match, 0, 0, 0)
  89
  90     # Check read miss
  91     command = 1
  92     key = 2
  93     data = 1
  94     match = 0
  95     yield from set_cam_entry(dut, command, key, data)
  96     yield from check_all(dut, key, data, match, 1, 0, 0)
  97
  98     # Check read hit
  99     command = 1
 100     key = 1
 101     data = 1
 102     match = 1
 103     yield from set_cam_entry(dut, command, key, data)
 104     yield from check_all(dut, key, data, match, 0, 0, 0)
 105
 106     # Check overwrite
 107     command = 2
 108     key = 2
 109     data = 5
 110     match = 0
 111     yield from set_cam_entry(dut, command, key, data)
 112     yield
 113     yield from check_all(dut, key, data, match, 0, 0, 0)
 114
 115     # Check read hit
 116     command = 1
 117     key = 2
 118     data = 5
 119     match = 1
 120     yield from set_cam_entry(dut, command, key, data)
 121     yield from check_all(dut, key, data, match, 0, 0, 0)
 122
 123     # Extra clock cycle for waveform
 124     yield
 125
 126 if __name__ == "__main__":
 127     dut = CamEntry(4, 4)
 128     run_simulation(dut, testbench(dut), vcd_name="Waveforms/cam_entry_test.vcd")
 129     print("CamEntry Unit Test Success")