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  17 From: Staf Verhaegen <staf@fibraservi.eu>
  18 To: libre-riscv-dev@lists.libre-riscv.org
  19 Date: Fri, 08 May 2020 19:23:35 +0200
  20 In-Reply-To: <CAPweEDzdkhVJuJ3_UqZTbd7i7vXJ5iiu3qz+LUBsFRJrzCcEmQ@mail.gmail.com>
  21 References: <CAPweEDw862-S1=Au1YbsKNy0629pa56eShp+2o_Avd96Auz8mw@mail.gmail.com>
  22  <9191058ea0912f2b508a6f73ea567e5f@f-cpu.org>
  23  <CAPweEDzdkhVJuJ3_UqZTbd7i7vXJ5iiu3qz+LUBsFRJrzCcEmQ@mail.gmail.com>
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  28 Subject: Re: [libre-riscv-dev] Debug port (was Re: minimum viable ASIC)
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  57 Luke Kenneth Casson Leighton schreef op vr 08-05-2020 om 17:55 [+0100]:
  58 > On Fri, May 8, 2020 at 4:27 PM <whygee@f-cpu.org> wrote:
  59 > > To me JTAG/TAP/debug port shine from its absence.
  60 >=20
  61 > yep good catch.  added.
  62
  63 I already have (alpha version) nmigen JTAG code: https://gitlab.com/Chips4M=
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