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  16 Message-ID: <803285a5aa4bed5be9c8d4bc5855f49174742f33.camel@fibraservi.eu>
  17 From: Staf Verhaegen <staf@fibraservi.eu>
  18 To: libre-riscv-dev@lists.libre-riscv.org
  19 Date: Wed, 20 May 2020 18:44:06 +0200
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  30 Subject: Re: [libre-riscv-dev] Debug port (was Re: minimum viable ASIC)
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  58
  59 Luke Kenneth Casson Leighton schreef op vr 08-05-2020 om 23:19 [+0100]:
  60 > ---crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma6=
  61 8
  62 >=20
  63 > On Fri, May 8, 2020 at 6:23 PM Staf Verhaegen <staf@fibraservi.eu> wrote:
  64 >=20
  65 > ah.  as a software engineer, the practice of using wildcard imports isan =
  66 extremely bad one.  i strongly advocate *not* getting into thehabit of doin=
  67 g "from nmigen import *" everywhere - it will make yourlife - and other use=
  68 rs lives - absolute hell when it comes to tryingto track and debug code.
  69 > minerva has a JTAG interface as well.  i corrected the practice ofusing "=
  70 import *" in this one
  71
  72 Would 'import nmigen as nm' work for you?I did not touch code for a few mon=
  73 ths and in the mean time I do use a more PEP compliant code style. But I am=
  74  annoyed by the individual list of things to import. For nmigen or Hurrican=
  75 e there is typically a few lines of these includes. When I change for examp=
  76 le a Pad to a Rectilinear I may have to update the import list. I don't see=
  77  value add of this and it annoys me a lot.So I am thinking of switching to =
  78 'import Hurricane as hur' and 'import nmigen as nm'To me the only valid rea=
  79 son for not using wild cards is that a later wild card import may replace s=
  80 omething you did import before; this is avoided by namespacing the import w=
  81 ith 'import ... as ...'.
  82 > it looks like the minerva team got a long way with that.  alsoprovided a =
  83 wishbone master interface:
  84 > https://git.libre-soc.org/?p=3Dsoc.git;a=3Dblob;f=3Dsrc/soc/minerva/units=
  85 /debug/wbmaster.py;h=3Ddb02af95b4eb3ef8ac25b348f3abaa2bcbe7d96f;hb=3Da54adc=
  86 b65bad37b398b11e33a824c7d08c5fe509
  87
  88 That code seems to focus on the debugging protocol over the JTAG interface =
  89 the lower level part seems to be missing.In debug/top.py:...
  90 # FIXME: figure out where JTAGTap is
  91 # from jtagtap import JTAGTap
  92
  93
  94 class JTAGTap:
  95     def __init__(self):
  96         raise NotImplementedError(
  97             "jtagtap package not found: figure out where JTAGTap is")
  98 ...
  99
 100 My JTAG interface does actually the low level part, the protocol has to be =
 101 done by the user on top of it. I do think I have a flexible way of adding e=
 102 xtra shift registers and jtag commands. I also do provide boundary scan for=
 103  the IO pins which should make PCB testing much easier (BTW, this was actua=
 104 lly the original use case for JTAG).
 105 greets,Staf.
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