2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Aki "lethalbit" Van Ness <aki@yosyshq.com> <aki@lethalbit.net>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/rtlil.h"
21 #include "kernel/register.h"
22 #include "kernel/sigtools.h"
23 #include "kernel/celltypes.h"
24 #include "kernel/cellaigs.h"
25 #include "kernel/log.h"
28 #include <unordered_map>
32 PRIVATE_NAMESPACE_BEGIN
41 // XXX(aki): TODO: this needs to be updated to us
42 // dict<T, V> and then coalesce_cells needs to be updated
43 // but for now for the PoC this looks to be sufficient
44 std::unordered_map
<std::string
, std::vector
<Cell
*>> _cells
{};
46 bool _include_connections
;
47 bool _include_attributes
;
48 bool _include_properties
;
50 string
escape_string(string str
) {
53 auto itr
= str
.begin();
55 for(; itr
!= str
.end(); ++itr
) {
87 // XXX(aki): I know this is far from ideal but i'm out of spoons and cant focus so
88 // it'll have to do for now,
89 void coalesce_cells(Module
* mod
)
91 for (auto cell
: mod
->cells()) {
92 const auto cell_type
= escape_string(RTLIL::unescape_id(cell
->type
));
94 if (_cells
.find(cell_type
) == _cells
.end())
95 _cells
.emplace(cell_type
, std::vector
<Cell
*>());
97 _cells
.at(cell_type
).push_back(cell
);
101 // XXX(aki): this is a lazy way to do this i know,,,
102 std::string
gen_indent(const uint16_t level
)
105 for (uint16_t i
= 0; i
<= level
; ++i
)
113 JnyWriter(std::ostream
&f
, bool use_selection
, bool connections
, bool attributes
, bool properties
) noexcept
:
114 f(f
), _use_selection(use_selection
),
115 _include_connections(connections
), _include_attributes(attributes
), _include_properties(properties
)
118 void write_metadata(Design
*design
, uint16_t indent_level
= 0)
120 log_assert(design
!= nullptr);
125 f
<< stringf(" \"generator\": \"%s\",\n", escape_string(yosys_version_str
).c_str());
126 // XXX(aki): Replace this with a proper version info eventually:tm:
127 f
<< " \"version\": \"0.0.0\",\n";
129 f
<< " \"features\": [";
132 if (_include_connections
) {
134 f
<< "\"connections\"";
137 if (_include_attributes
) {
141 f
<< "\"attributes\"";
144 if (_include_properties
) {
148 f
<< "\"properties\"";
153 f
<< " \"modules\": [\n";
156 for (auto mod
: _use_selection
? design
->selected_modules() : design
->modules()) {
159 write_module(mod
, indent_level
+ 2);
168 void write_sigspec(const RTLIL::SigSpec
& sig
, uint16_t indent_level
= 0) {
169 const auto _indent
= gen_indent(indent_level
);
171 f
<< _indent
<< " {\n";
172 f
<< _indent
<< " \"width\": \"" << sig
.size() << "\",\n";
173 f
<< _indent
<< " \"type\": \"";
177 } else if (sig
.is_chunk()) {
179 } else if (sig
.is_bit()) {
186 f
<< _indent
<< " \"const\": ";
187 if (sig
.has_const()) {
195 f
<< _indent
<< " }";
198 void write_mod_conn(const std::pair
<RTLIL::SigSpec
, RTLIL::SigSpec
>& conn
, uint16_t indent_level
= 0) {
199 const auto _indent
= gen_indent(indent_level
);
200 f
<< _indent
<< " {\n";
201 f
<< _indent
<< " \"signals\": [\n";
203 write_sigspec(conn
.first
, indent_level
+ 2);
205 write_sigspec(conn
.second
, indent_level
+ 2);
208 f
<< _indent
<< " ]\n";
209 f
<< _indent
<< " }";
212 void write_cell_conn(const std::pair
<RTLIL::IdString
, RTLIL::SigSpec
>& sig
, uint16_t indent_level
= 0) {
213 const auto _indent
= gen_indent(indent_level
);
214 f
<< _indent
<< " {\n";
215 f
<< _indent
<< " \"name\": \"" << escape_string(RTLIL::unescape_id(sig
.first
)) << "\",\n";
216 f
<< _indent
<< " \"signals\": [\n";
218 write_sigspec(sig
.second
, indent_level
+ 2);
221 f
<< _indent
<< " ]\n";
222 f
<< _indent
<< " }";
225 void write_module(Module
* mod
, uint16_t indent_level
= 0) {
226 log_assert(mod
!= nullptr);
230 const auto _indent
= gen_indent(indent_level
);
232 f
<< _indent
<< "{\n";
233 f
<< stringf(" %s\"name\": \"%s\",\n", _indent
.c_str(), escape_string(RTLIL::unescape_id(mod
->name
)).c_str());
234 f
<< _indent
<< " \"cell_sorts\": [\n";
236 bool first_sort
{true};
237 for (auto& sort
: _cells
) {
240 write_cell_sort(sort
, indent_level
+ 2);
245 f
<< _indent
<< " ]";
246 if (_include_connections
) {
247 f
<< ",\n" << _indent
<< " \"connections\": [\n";
249 bool first_conn
{true};
250 for (const auto& conn
: mod
->connections()) {
254 write_mod_conn(conn
, indent_level
+ 2);
259 f
<< _indent
<< " ]";
261 if (_include_attributes
) {
262 f
<< ",\n" << _indent
<< " \"attributes\": {\n";
264 write_prams(mod
->attributes
, indent_level
+ 2);
267 f
<< _indent
<< " }";
269 f
<< "\n" << _indent
<< "}";
272 void write_cell_ports(RTLIL::Cell
* port_cell
, uint64_t indent_level
= 0) {
273 const auto _indent
= gen_indent(indent_level
);
275 bool first_port
{true};
276 for (auto con
: port_cell
->connections()) {
280 f
<< _indent
<< " {\n";
281 f
<< stringf(" %s\"name\": \"%s\",\n", _indent
.c_str(), escape_string(RTLIL::unescape_id(con
.first
)).c_str());
282 f
<< _indent
<< " \"direction\": \"";
283 if (port_cell
->input(con
.first
))
285 if (port_cell
->input(con
.first
))
288 if (con
.second
.size() == 1)
289 f
<< _indent
<< " \"range\": [0, 0]\n";
291 f
<< stringf(" %s\"range\": [%d, %d]\n", _indent
.c_str(), con
.second
.size(), 0);
292 f
<< _indent
<< " }";
300 void write_cell_sort(std::pair
<const std::string
, std::vector
<Cell
*>>& sort
, uint16_t indent_level
= 0) {
301 const auto port_cell
= sort
.second
.front();
302 const auto _indent
= gen_indent(indent_level
);
304 f
<< _indent
<< "{\n";
305 f
<< stringf(" %s\"type\": \"%s\",\n", _indent
.c_str(), sort
.first
.c_str());
306 f
<< _indent
<< " \"ports\": [\n";
308 write_cell_ports(port_cell
, indent_level
+ 2);
310 f
<< _indent
<< " ],\n" << _indent
<< " \"cells\": [\n";
312 bool first_cell
{true};
313 for (auto& cell
: sort
.second
) {
317 write_cell(cell
, indent_level
+ 2);
323 f
<< _indent
<< " ]\n";
327 void write_param_val(const Const
& v
) {
328 if ((v
.flags
& RTLIL::ConstFlags::CONST_FLAG_STRING
) == RTLIL::ConstFlags::CONST_FLAG_STRING
) {
329 const auto str
= v
.decode_string();
331 // XXX(aki): TODO, uh, yeah
333 f
<< "\"" << escape_string(str
) << "\"";
334 } else if ((v
.flags
& RTLIL::ConstFlags::CONST_FLAG_SIGNED
) == RTLIL::ConstFlags::CONST_FLAG_SIGNED
) {
335 f
<< stringf("\"%dsd %d\"", v
.size(), v
.as_int(true));
336 } else if ((v
.flags
& RTLIL::ConstFlags::CONST_FLAG_REAL
) == RTLIL::ConstFlags::CONST_FLAG_REAL
) {
339 f
<< "\"" << escape_string(v
.as_string()) << "\"";
343 void write_prams(dict
<RTLIL::IdString
, RTLIL::Const
>& params
, uint16_t indent_level
= 0) {
344 const auto _indent
= gen_indent(indent_level
);
346 bool first_param
{true};
347 for (auto& param
: params
) {
350 const auto param_val
= param
.second
;
351 if (!param_val
.empty()) {
352 f
<< stringf(" %s\"%s\": ", _indent
.c_str(), escape_string(RTLIL::unescape_id(param
.first
)).c_str());
353 write_param_val(param_val
);
355 f
<< stringf(" %s\"%s\": true", _indent
.c_str(), escape_string(RTLIL::unescape_id(param
.first
)).c_str());
362 void write_cell(Cell
* cell
, uint16_t indent_level
= 0) {
363 const auto _indent
= gen_indent(indent_level
);
364 log_assert(cell
!= nullptr);
366 f
<< _indent
<< " {\n";
367 f
<< stringf(" %s\"name\": \"%s\"", _indent
.c_str(), escape_string(RTLIL::unescape_id(cell
->name
)).c_str());
369 if (_include_connections
) {
370 f
<< ",\n" << _indent
<< " \"connections\": [\n";
372 bool first_conn
{true};
373 for (const auto& conn
: cell
->connections()) {
377 write_cell_conn(conn
, indent_level
+ 2);
383 f
<< _indent
<< " ]";
386 if (_include_attributes
) {
387 f
<< ",\n" << _indent
<< " \"attributes\": {\n";
389 write_prams(cell
->attributes
, indent_level
+ 2);
392 f
<< _indent
<< " }";
395 if (_include_properties
) {
396 f
<< ",\n" << _indent
<< " \"parameters\": {\n";
398 write_prams(cell
->parameters
, indent_level
+ 2);
401 f
<< _indent
<< " }";
404 f
<< "\n" << _indent
<< " }";
408 struct JnyBackend
: public Backend
{
409 JnyBackend() : Backend("jny", "generate design metadata") { }
410 void help() override
{
411 // XXX(aki): TODO: explicitly document the JSON schema
412 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
414 log(" jny [options] [selection]\n");
416 log(" -connections\n");
417 log(" Include connection information in the netlist output.\n");
419 log(" -attributes\n");
420 log(" Include attributed information in the netlist output.\n");
422 log(" -properties\n");
423 log(" Include property information in the netlist output.\n");
425 log("Write a JSON metadata for the current design\n");
430 void execute(std::ostream
*&f
, std::string filename
, std::vector
<std::string
> args
, RTLIL::Design
*design
) override
{
432 bool connections
{false};
433 bool attributes
{false};
434 bool properties
{false};
437 for (; argidx
< args
.size(); argidx
++) {
438 if (args
[argidx
] == "-connections") {
443 if (args
[argidx
] == "-attributes") {
448 if (args
[argidx
] == "-properties") {
455 extra_args(f
, filename
, args
, argidx
);
457 log_header(design
, "Executing jny backend.\n");
459 JnyWriter
jny_writer(*f
, false, connections
, attributes
, properties
);
460 jny_writer
.write_metadata(design
);
466 struct JnyPass
: public Pass
{
467 JnyPass() : Pass("jny", "write design and metadata") { }
469 void help() override
{
470 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
472 log(" jny [options] [selection]\n");
474 log("Write a JSON netlist metadata for the current design\n");
476 log(" -o <filename>\n");
477 log(" write to the specified file.\n");
479 log(" -connections\n");
480 log(" Include connection information in the netlist output.\n");
482 log(" -attributes\n");
483 log(" Include attributed information in the netlist output.\n");
485 log(" -properties\n");
486 log(" Include property information in the netlist output.\n");
488 log("See 'help write_jny' for a description of the JSON format used.\n");
491 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) override
{
492 std::string filename
{};
494 bool connections
{false};
495 bool attributes
{false};
496 bool properties
{false};
499 for (; argidx
< args
.size(); argidx
++) {
500 if (args
[argidx
] == "-o" && argidx
+1 < args
.size()) {
501 filename
= args
[++argidx
];
505 if (args
[argidx
] == "-connections") {
510 if (args
[argidx
] == "-attributes") {
515 if (args
[argidx
] == "-properties") {
522 extra_args(args
, argidx
, design
);
525 std::stringstream buf
;
527 if (!filename
.empty()) {
528 rewrite_filename(filename
);
529 std::ofstream
*ff
= new std::ofstream
;
530 ff
->open(filename
.c_str(), std::ofstream::trunc
);
533 log_error("Can't open file `%s' for writing: %s\n", filename
.c_str(), strerror(errno
));
541 JnyWriter
jny_writer(*f
, false, connections
, attributes
, properties
);
542 jny_writer
.write_metadata(design
);
544 if (!filename
.empty()) {
547 log("%s", buf
.str().c_str());
553 PRIVATE_NAMESPACE_END