2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Aki "lethalbit" Van Ness <aki@yosyshq.com> <aki@lethalbit.net>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/rtlil.h"
21 #include "kernel/register.h"
22 #include "kernel/sigtools.h"
23 #include "kernel/celltypes.h"
24 #include "kernel/cellaigs.h"
25 #include "kernel/log.h"
28 #include <unordered_map>
32 PRIVATE_NAMESPACE_BEGIN
40 std::unordered_map
<std::string
, std::vector
<Cell
*>> _cells
{};
42 bool _include_connections
;
43 bool _include_attributes
;
44 bool _include_properties
;
46 string
escape_string(string str
) {
49 auto itr
= str
.begin();
51 for(; itr
!= str
.end(); ++itr
) {
96 // XXX(aki): I know this is far from ideal but i'm out of spoons and cant focus so
97 // it'll have to do for now,
98 void coalesce_cells(Module
* mod
)
100 for (auto cell
: mod
->cells()) {
101 const auto cell_type
= escape_string(RTLIL::unescape_id(cell
->type
));
103 if (_cells
.find(cell_type
) == _cells
.end())
104 _cells
.emplace(cell_type
, std::vector
<Cell
*>());
106 _cells
.at(cell_type
).push_back(cell
);
110 // XXX(aki): this is a lazy way to do this i know,,,
111 std::string
gen_indent(const uint16_t level
)
114 for (uint16_t i
= 0; i
<= level
; ++i
)
122 JnyWriter(std::ostream
&f
, bool use_selection
, bool connections
, bool attributes
, bool properties
) noexcept
:
123 f(f
), _use_selection(use_selection
),
124 _include_connections(connections
), _include_attributes(attributes
), _include_properties(properties
)
127 void write_metadata(Design
*design
, uint16_t indent_level
= 0)
129 log_assert(design
!= nullptr);
134 f
<< stringf(" \"generator\": \"%s\",\n", escape_string(yosys_version_str
).c_str());
135 // XXX(aki): Replace this with a proper version info eventually:tm:
136 f
<< " \"version\": \"0.0.0\",\n";
138 f
<< " \"features\": [";
141 if (_include_connections
) {
143 f
<< "\"connections\"";
146 if (_include_attributes
) {
150 f
<< "\"attributes\"";
153 if (_include_properties
) {
157 f
<< "\"properties\"";
162 f
<< " \"modules\": [\n";
165 for (auto mod
: _use_selection
? design
->selected_modules() : design
->modules()) {
168 write_module(mod
, indent_level
+ 2);
177 void write_sigspec(const RTLIL::SigSpec
& sig
, uint16_t indent_level
= 0) {
178 const auto _indent
= gen_indent(indent_level
);
180 f
<< _indent
<< " {\n";
181 f
<< _indent
<< " \"width\": \"" << sig
.size() << "\",\n";
182 f
<< _indent
<< " \"type\": \"";
186 } else if (sig
.is_chunk()) {
188 } else if (sig
.is_bit()) {
195 f
<< _indent
<< " \"const\": ";
196 if (sig
.has_const()) {
204 f
<< _indent
<< " }";
207 void write_mod_conn(const std::pair
<RTLIL::SigSpec
, RTLIL::SigSpec
>& conn
, uint16_t indent_level
= 0) {
208 const auto _indent
= gen_indent(indent_level
);
209 f
<< _indent
<< " {\n";
210 f
<< _indent
<< " \"signals\": [\n";
212 write_sigspec(conn
.first
, indent_level
+ 2);
214 write_sigspec(conn
.second
, indent_level
+ 2);
217 f
<< _indent
<< " ]\n";
218 f
<< _indent
<< " }";
221 void write_cell_conn(const std::pair
<RTLIL::IdString
, RTLIL::SigSpec
>& sig
, uint16_t indent_level
= 0) {
222 const auto _indent
= gen_indent(indent_level
);
223 f
<< _indent
<< " {\n";
224 f
<< _indent
<< " \"name\": \"" << escape_string(RTLIL::unescape_id(sig
.first
)) << "\",\n";
225 f
<< _indent
<< " \"signals\": [\n";
227 write_sigspec(sig
.second
, indent_level
+ 2);
230 f
<< _indent
<< " ]\n";
231 f
<< _indent
<< " }";
234 void write_module(Module
* mod
, uint16_t indent_level
= 0) {
235 log_assert(mod
!= nullptr);
239 const auto _indent
= gen_indent(indent_level
);
241 f
<< _indent
<< "{\n";
242 f
<< stringf(" %s\"name\": \"%s\",\n", _indent
.c_str(), escape_string(RTLIL::unescape_id(mod
->name
)).c_str());
243 f
<< _indent
<< " \"cell_sorts\": [\n";
245 bool first_sort
{true};
246 for (auto& sort
: _cells
) {
249 write_cell_sort(sort
, indent_level
+ 2);
254 f
<< _indent
<< " ]";
255 if (_include_connections
) {
256 f
<< ",\n" << _indent
<< " \"connections\": [\n";
258 bool first_conn
{true};
259 for (const auto& conn
: mod
->connections()) {
263 write_mod_conn(conn
, indent_level
+ 2);
268 f
<< _indent
<< " ]";
270 if (_include_attributes
) {
271 f
<< ",\n" << _indent
<< " \"attributes\": {\n";
273 write_prams(mod
->attributes
, indent_level
+ 2);
276 f
<< _indent
<< " }";
278 f
<< "\n" << _indent
<< "}";
281 void write_cell_ports(RTLIL::Cell
* port_cell
, uint64_t indent_level
= 0) {
282 const auto _indent
= gen_indent(indent_level
);
284 bool first_port
{true};
285 for (auto con
: port_cell
->connections()) {
289 f
<< _indent
<< " {\n";
290 f
<< stringf(" %s\"name\": \"%s\",\n", _indent
.c_str(), escape_string(RTLIL::unescape_id(con
.first
)).c_str());
291 f
<< _indent
<< " \"direction\": \"";
292 if (port_cell
->input(con
.first
))
294 if (port_cell
->input(con
.first
))
297 if (con
.second
.size() == 1)
298 f
<< _indent
<< " \"range\": [0, 0]\n";
300 f
<< stringf(" %s\"range\": [%d, %d]\n", _indent
.c_str(), con
.second
.size(), 0);
301 f
<< _indent
<< " }";
309 void write_cell_sort(std::pair
<const std::string
, std::vector
<Cell
*>>& sort
, uint16_t indent_level
= 0) {
310 const auto port_cell
= sort
.second
.front();
311 const auto _indent
= gen_indent(indent_level
);
313 f
<< _indent
<< "{\n";
314 f
<< stringf(" %s\"type\": %s,\n", _indent
.c_str(), sort
.first
.c_str());
315 f
<< _indent
<< " \"ports\": [\n";
317 write_cell_ports(port_cell
, indent_level
+ 2);
319 f
<< _indent
<< " ],\n" << _indent
<< " \"cells\": [\n";
321 bool first_cell
{true};
322 for (auto& cell
: sort
.second
) {
326 write_cell(cell
, indent_level
+ 2);
332 f
<< _indent
<< " ]\n";
336 void write_param_val(const Const
& v
) {
337 if ((v
.flags
& RTLIL::ConstFlags::CONST_FLAG_STRING
) == RTLIL::ConstFlags::CONST_FLAG_STRING
) {
338 const auto str
= v
.decode_string();
340 // XXX(aki): TODO, uh, yeah
342 f
<< "\"" << escape_string(str
) << "\"";
343 } else if ((v
.flags
& RTLIL::ConstFlags::CONST_FLAG_SIGNED
) == RTLIL::ConstFlags::CONST_FLAG_SIGNED
) {
344 f
<< stringf("\"%dsd %d\"", v
.size(), v
.as_int(true));
345 } else if ((v
.flags
& RTLIL::ConstFlags::CONST_FLAG_REAL
) == RTLIL::ConstFlags::CONST_FLAG_REAL
) {
348 f
<< "\"" << escape_string(v
.as_string()) << "\"";
352 void write_prams(dict
<RTLIL::IdString
, RTLIL::Const
>& params
, uint16_t indent_level
= 0) {
353 const auto _indent
= gen_indent(indent_level
);
355 bool first_param
{true};
356 for (auto& param
: params
) {
359 const auto param_val
= param
.second
;
360 if (!param_val
.empty()) {
361 f
<< stringf(" %s\"%s\": ", _indent
.c_str(), escape_string(RTLIL::unescape_id(param
.first
)).c_str());
362 write_param_val(param_val
);
364 f
<< stringf(" %s\"%s\": true", _indent
.c_str(), escape_string(RTLIL::unescape_id(param
.first
)).c_str());
371 void write_cell(Cell
* cell
, uint16_t indent_level
= 0) {
372 const auto _indent
= gen_indent(indent_level
);
373 log_assert(cell
!= nullptr);
375 f
<< _indent
<< " {\n";
376 f
<< stringf(" %s\"name\": \"%s\"", _indent
.c_str(), escape_string(RTLIL::unescape_id(cell
->name
)).c_str());
378 if (_include_connections
) {
379 f
<< ",\n" << _indent
<< " \"connections\": [\n";
381 bool first_conn
{true};
382 for (const auto& conn
: cell
->connections()) {
386 write_cell_conn(conn
, indent_level
+ 2);
392 f
<< _indent
<< " ]";
395 if (_include_attributes
) {
396 f
<< ",\n" << _indent
<< " \"attributes\": {\n";
398 write_prams(cell
->attributes
, indent_level
+ 2);
401 f
<< _indent
<< " }";
404 if (_include_properties
) {
405 f
<< ",\n" << _indent
<< " \"parameters\": {\n";
407 write_prams(cell
->parameters
, indent_level
+ 2);
410 f
<< _indent
<< " }";
413 f
<< "\n" << _indent
<< " }";
417 struct JnyBackend
: public Backend
{
418 JnyBackend() : Backend("jny", "generate design metadata") { }
419 void help() override
{
420 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
422 log(" jny [options] [selection]\n");
424 log(" -connections\n");
425 log(" Include connection information in the netlist output.\n");
427 log(" -attributes\n");
428 log(" Include attributed information in the netlist output.\n");
430 log(" -properties\n");
431 log(" Include property information in the netlist output.\n");
433 log("Write a JSON metadata for the current design\n");
438 void execute(std::ostream
*&f
, std::string filename
, std::vector
<std::string
> args
, RTLIL::Design
*design
) override
{
440 bool connections
{false};
441 bool attributes
{false};
442 bool properties
{false};
445 for (; argidx
< args
.size(); argidx
++) {
446 if (args
[argidx
] == "-connections") {
451 if (args
[argidx
] == "-attributes") {
456 if (args
[argidx
] == "-properties") {
463 extra_args(f
, filename
, args
, argidx
);
465 log_header(design
, "Executing jny backend.\n");
467 JnyWriter
jny_writer(*f
, false, connections
, attributes
, properties
);
468 jny_writer
.write_metadata(design
);
474 struct JnyPass
: public Pass
{
475 JnyPass() : Pass("jny", "write design and metadata") { }
477 void help() override
{
478 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
480 log(" jny [options] [selection]\n");
482 log("Write a JSON netlist metadata for the current design\n");
484 log(" -o <filename>\n");
485 log(" write to the specified file.\n");
487 log(" -connections\n");
488 log(" Include connection information in the netlist output.\n");
490 log(" -attributes\n");
491 log(" Include attributed information in the netlist output.\n");
493 log(" -properties\n");
494 log(" Include property information in the netlist output.\n");
496 log("See 'help write_jny' for a description of the JSON format used.\n");
499 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) override
{
500 std::string filename
{};
502 bool connections
{false};
503 bool attributes
{false};
504 bool properties
{false};
507 for (; argidx
< args
.size(); argidx
++) {
508 if (args
[argidx
] == "-o" && argidx
+1 < args
.size()) {
509 filename
= args
[++argidx
];
513 if (args
[argidx
] == "-connections") {
518 if (args
[argidx
] == "-attributes") {
523 if (args
[argidx
] == "-properties") {
530 extra_args(args
, argidx
, design
);
533 std::stringstream buf
;
535 if (!filename
.empty()) {
536 rewrite_filename(filename
);
537 std::ofstream
*ff
= new std::ofstream
;
538 ff
->open(filename
.c_str(), std::ofstream::trunc
);
541 log_error("Can't open file `%s' for writing: %s\n", filename
.c_str(), strerror(errno
));
549 JnyWriter
jny_writer(*f
, false, connections
, attributes
, properties
);
550 jny_writer
.write_metadata(design
);
552 if (!filename
.empty()) {
555 log("%s", buf
.str().c_str());
561 PRIVATE_NAMESPACE_END