1 # See LICENSE for license details.
21 supervisor_trap_entry:
22 j supervisor_trap_entry
25 hypervisor_trap_entry:
26 j hypervisor_trap_entry
67 li t0, MSTATUS_MPP; csrc mstatus, t0 # run tests in user mode
68 li t0, MSTATUS_MPIE; csrs mstatus, t0 # enable interrupts in user mode
69 li t0, MSTATUS_FS; csrs mstatus, t0 # enable FPU
70 li t0, MSTATUS_XS; csrs mstatus, t0 # enable accelerator
74 # make sure processor supports RV64 if this was compiled for RV64
86 ## if that didn't stick, we don't have a FPU, so don't initialize it
91 #ifdef __riscv_hard_float
129 # initialize global pointer
137 # for now, assume only 1 core
141 # give each core 128KB of stack + TLS
156 SREG x1, 1*REGBYTES(sp)
157 SREG x2, 2*REGBYTES(sp)
158 SREG x3, 3*REGBYTES(sp)
159 SREG x4, 4*REGBYTES(sp)
160 SREG x5, 5*REGBYTES(sp)
161 SREG x6, 6*REGBYTES(sp)
162 SREG x7, 7*REGBYTES(sp)
163 SREG x8, 8*REGBYTES(sp)
164 SREG x9, 9*REGBYTES(sp)
165 SREG x10, 10*REGBYTES(sp)
166 SREG x11, 11*REGBYTES(sp)
167 SREG x12, 12*REGBYTES(sp)
168 SREG x13, 13*REGBYTES(sp)
169 SREG x14, 14*REGBYTES(sp)
170 SREG x15, 15*REGBYTES(sp)
171 SREG x16, 16*REGBYTES(sp)
172 SREG x17, 17*REGBYTES(sp)
173 SREG x18, 18*REGBYTES(sp)
174 SREG x19, 19*REGBYTES(sp)
175 SREG x20, 20*REGBYTES(sp)
176 SREG x21, 21*REGBYTES(sp)
177 SREG x22, 22*REGBYTES(sp)
178 SREG x23, 23*REGBYTES(sp)
179 SREG x24, 24*REGBYTES(sp)
180 SREG x25, 25*REGBYTES(sp)
181 SREG x26, 26*REGBYTES(sp)
182 SREG x27, 27*REGBYTES(sp)
183 SREG x28, 28*REGBYTES(sp)
184 SREG x29, 29*REGBYTES(sp)
185 SREG x30, 30*REGBYTES(sp)
186 SREG x31, 31*REGBYTES(sp)
194 LREG x1, 1*REGBYTES(sp)
195 LREG x2, 2*REGBYTES(sp)
196 LREG x3, 3*REGBYTES(sp)
197 LREG x4, 4*REGBYTES(sp)
198 LREG x5, 5*REGBYTES(sp)
199 LREG x6, 6*REGBYTES(sp)
200 LREG x7, 7*REGBYTES(sp)
201 LREG x8, 8*REGBYTES(sp)
202 LREG x9, 9*REGBYTES(sp)
203 LREG x10, 10*REGBYTES(sp)
204 LREG x11, 11*REGBYTES(sp)
205 LREG x12, 12*REGBYTES(sp)
206 LREG x13, 13*REGBYTES(sp)
207 LREG x14, 14*REGBYTES(sp)
208 LREG x15, 15*REGBYTES(sp)
209 LREG x16, 16*REGBYTES(sp)
210 LREG x17, 17*REGBYTES(sp)
211 LREG x18, 18*REGBYTES(sp)
212 LREG x19, 19*REGBYTES(sp)
213 LREG x20, 20*REGBYTES(sp)
214 LREG x21, 21*REGBYTES(sp)
215 LREG x22, 22*REGBYTES(sp)
216 LREG x23, 23*REGBYTES(sp)
217 LREG x24, 24*REGBYTES(sp)
218 LREG x25, 25*REGBYTES(sp)
219 LREG x26, 26*REGBYTES(sp)
220 LREG x27, 27*REGBYTES(sp)
221 LREG x28, 28*REGBYTES(sp)
222 LREG x29, 29*REGBYTES(sp)
223 LREG x30, 30*REGBYTES(sp)
224 LREG x31, 31*REGBYTES(sp)
229 .section ".tdata.begin"
233 .section ".tdata.end"