bootrom/sdboot/include/riscv_test_defaults.h

   1 // See LICENSE for license details.
   2 #ifndef _RISCV_TEST_DEFAULTS_H
   3 #define _RISCV_TEST_DEFAULTS_H
   4
   5 #define TESTNUM x28
   6 #define TESTBASE 0x4000
   7
   8 #define RVTEST_RV32U \
   9   .macro init; \
  10   .endm
  11
  12 #define RVTEST_RV64U \
  13   .macro init; \
  14   .endm
  15
  16 #define RVTEST_RV32UF \
  17   .macro init; \
  18   /* If FPU exists, initialize FCSR. */ \
  19   csrr t0, misa; \
  20   andi t0, t0, 1 << ('F' - 'A'); \
  21   beqz t0, 1f; \
  22   /* Enable FPU if it exists. */ \
  23   li t0, MSTATUS_FS; \
  24   csrs mstatus, t0; \
  25   fssr x0; \
  26 1: ; \
  27   .endm
  28
  29 #define RVTEST_RV64UF \
  30   .macro init; \
  31   /* If FPU exists, initialize FCSR. */ \
  32   csrr t0, misa; \
  33   andi t0, t0, 1 << ('F' - 'A'); \
  34   beqz t0, 1f; \
  35   /* Enable FPU if it exists. */ \
  36   li t0, MSTATUS_FS; \
  37   csrs mstatus, t0; \
  38   fssr x0; \
  39 1: ; \
  40   .endm
  41
  42 #define RVTEST_CODE_BEGIN \
  43   .section .text.init; \
  44   .globl _prog_start; \
  45 _prog_start: \
  46   init;
  47
  48 #define RVTEST_CODE_END \
  49   unimp
  50
  51 #define RVTEST_PASS \
  52   fence; \
  53   li t0, TESTBASE; \
  54   li t1, 0x5555; \
  55   sw t1, 0(t0); \
  56 1: \
  57   j 1b;
  58
  59 #define RVTEST_FAIL \
  60   li t0, TESTBASE; \
  61   li t1, 0x3333; \
  62   slli a0, a0, 16; \
  63   add a0, a0, t1; \
  64   sw a0, 0(t0); \
  65 1: \
  66   j 1b;
  67
  68 #define EXTRA_DATA
  69
  70 #define RVTEST_DATA_BEGIN \
  71   EXTRA_DATA \
  72   .align 4; .global begin_signature; begin_signature:
  73
  74 #define RVTEST_DATA_END \
  75   _msg_init: .asciz "RUN\r\n"; \
  76   _msg_pass: .asciz "PASS"; \
  77   _msg_fail: .asciz "FAIL "; \
  78   _msg_end: .asciz "\r\n"; \
  79   .align 4; .global end_signature; end_signature:
  80
  81 #endif /* _RISCV_TEST_DEFAULTS_H */